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[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k

Description: 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Platform: | Size: 253952 | Author: 周小川 | Hits:

[Other Embeded program] SKRETD(low_power)

Description: 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Platform: | Size: 380928 | Author: xialu | Hits:

[Communication-Mobile] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Platform: | Size: 154624 | Author: | Hits:

[Program doc] Viterbi

Description: 三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Platform: | Size: 451584 | Author: helei_zju | Hits:

[Communication-Mobile] Viterbi

Description: 卷积码（2，1，6），完整的工程文件，已经调试通过-Convolutional code (2,1,6), complete engineering documents have been debugging through
Platform: | Size: 47104 | Author: jishanyi | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: VHDL 程序，实现vertibe的编码和解码。-VHDL procedures vertibe realize the encoding and decoding.
Platform: | Size: 2048 | Author: 左麟 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[Compress-Decompress algrithms] 216Viterbi

Description: （2，1，6）格式的viterbi译码，软判决，完全的工程文件，可以直接应用于项目。-(2,1,6) format viterbi decoding, soft decision, a complete project file can be directly applied to the project.
Platform: | Size: 47104 | Author: water206 | Hits:

[Communication] 217viterbi

Description: viterbi译码算法的vhdl程序，有注释和各个模块的详细说明。是一篇完整的硕士论文，有源码-viterbi decoding algorithm of VHDL procedures, has comments and a detailed description of each module. Is a complete master
Platform: | Size: 563200 | Author: Wayne | Hits:

[Software Engineering] viterbi

Description: 适合高速Viterbi译码器的hdl的设计与实现-脢脢 潞 脧 赂 脽脣脵Viterbi脪毛脗毛脝 梅 渭脛hdl渭脛脡猫 录 脝脫毛脢渭脧脰
Platform: | Size: 443392 | Author: mediative | Hits:

[Program doc] viterbi

Description: 基于XilinxFPGA的高速Viterbi回溯译码器-Based on retrospective XilinxFPGA high-speed Viterbi decoder
Platform: | Size: 198656 | Author: mediative | Hits:

[Program doc] viterbi

Description: 高速Viterbi处理器的并行算法和结构-High-speed Viterbi processor parallel algorithm and structure
Platform: | Size: 250880 | Author: mediative | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Platform: | Size: 256000 | Author: mediative | Hits:

[Program doc] viterbi

Description: 维特比译码器的asic设计的相关论文-Viterbi Decoder asic design related articles
Platform: | Size: 277504 | Author: mediative | Hits:

[VHDL-FPGA-Verilog] husw

Description: 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Platform: | Size: 1024 | Author: hsw0320 | Hits:

[VHDL-FPGA-Verilog] Viterbi

Description: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Platform: | Size: 8192 | Author: 蔡敏 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Platform: | Size: 3072 | Author: xiongherui | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 对于语音信号的Viterbi算法的简单仿真实现 在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
Platform: | Size: 1024 | Author: 房先生 | Hits:

[VHDL-FPGA-Verilog] Viterbi

Description: 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
Platform: | Size: 148480 | Author: 飞熊 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Platform: | Size: 92160 | Author: Fengxiaodong | Hits:
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