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[Embeded-SCM Developviterbi_decoder_sources_code_verilog

Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: | Size: 44082 | Author: 林四昆 | Hits:

[Other resourceviterbi

Description: (2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过
Platform: | Size: 10748 | Author: rxl | Hits:

[Software Engineeringviterbi

Description: 适合高速Viterbi译码器的hdl的设计与实现
Platform: | Size: 443516 | Author: mediative | Hits:

[Embeded-SCM Developviterbi_decoder_sources_code_verilog

Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: | Size: 44032 | Author: 林四昆 | Hits:

[VHDL-FPGA-Verilogviterbi

Description: VHDL 程序,实现vertibe的编码和解码。-VHDL procedures vertibe realize the encoding and decoding.
Platform: | Size: 2048 | Author: 左麟 | Hits:

[VHDL-FPGA-Verilogviterbi

Description: (2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
Platform: | Size: 10240 | Author: rxl | Hits:

[Software Engineeringviterbi

Description: 适合高速Viterbi译码器的hdl的设计与实现-脢脢 潞 脧 赂 脽脣脵Viterbi脪毛脗毛脝 梅 渭脛hdl渭脛脡猫 录 脝脫毛脢渭脧脰
Platform: | Size: 443392 | Author: mediative | Hits:

[VHDL-FPGA-Verilogviterbi

Description:
Platform: | Size: 227328 | Author: deng | Hits:

[3G develophdl

Description:
Platform: | Size: 143360 | Author: mike | Hits:

[VHDL-FPGA-Verilogviterbi

Description: 这是一个用VERILOG HDL语言编写的viterbi译码程序-This is a language VERILOG HDL by the viterbi decoding process
Platform: | Size: 2048 | Author: chenxiaoming | Hits:

[VHDL-FPGA-Verilogviterbidecoder

Description: viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL (3,1,7)zero tail conventional code
Platform: | Size: 5120 | Author: zhouli | Hits:

[Modem programhdlcoderviterbi

Description: hdl coder viterbi hdl coder viterbi hdl coder viterbi-hdl coder viterbi hdl coder viterbi hdl coder viterbi hdl coder viterbi
Platform: | Size: 21504 | Author: oudjani | Hits:

[VHDL-FPGA-Verilogviterbi

Description: This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.-This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
Platform: | Size: 654336 | Author: Nagendran | Hits:

[Modem programVITERBI

Description: In this case is a viterbi algorithm code for decoding the convolutional code, using verilog HDL language. This code provide the method of deconvolution of the convolutional code
Platform: | Size: 2048 | Author: kimdaeyoung | Hits:

[VHDL-FPGA-Verilogverilog-juanjima

Description: 卷积码是一种重要的前向纠错信道编码方式,其纠错性能常常优于分组码,且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog  HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块,译码器采用全并行结构,译码速度快-Convolutional code is an important forward error correction channel coding method, and its error correction performance is often better than the block code, and (2,1,7) convolutional code has been used in modern satellite communication system. Viterbi decoding algorithm can maximize the performance of convolutional codes. Here is the Verilog HDL design (2,1,7) convolutional code encoder module and decoder module based on Viterbi algorithm, the decoder is designed using the parallel structure and the decoding speed is fast.
Platform: | Size: 10240 | Author: 邓博于、 | Hits:

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