Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - viterbi decoder verilog code

Search list

[VHDL-FPGA-Verilog] viterbi

Description: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Platform: | Size: 3072 | Author: xiongherui | Hits:

[VHDL-FPGA-Verilog] viterbidecoder

Description: viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
Platform: | Size: 5120 | Author: zhouli | Hits:

[VHDL-FPGA-Verilog] viterbi_for_bch

Description: Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
Platform: | Size: 1024 | Author: shahifaqeer | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: verilog code for viterbi encoder and decoder
Platform: | Size: 13312 | Author: kamran | Hits:

[VHDL-FPGA-Verilog] Control

Description: 维特比译码器控制器部分Verilog代码-The controller part of the Viterbi decoder in Verilog code
Platform: | Size: 1024 | Author: 王阳 | Hits:

[VHDL-FPGA-Verilog] viterbi_decoder_axi4s

Description: Viterbi译码器的verilog代码和测试-Verilog code and testing of the Viterbi decoder
Platform: | Size: 18925568 | Author: 李雪利 | Hits:

[Post-TeleCom sofeware systems] newViterbi217

Description: 基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct
Platform: | Size: 18432 | Author: logic | Hits:

[VHDL-FPGA-Verilog] Enc_With_Punc---2011-11-28-v3.0

Description: Viterbi 译码打孔和去打孔代码, ,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
Platform: | Size: 2496512 | Author: | Hits:

[VHDL-FPGA-Verilog] viterbideoderupdated

Description: Viterbi decoder source code is in verilog with CRCv-Viterbi decoder source code is in verilog with CRCv
Platform: | Size: 2048 | Author: hr | Hits:

[VHDL-FPGA-Verilog] verilog-juanjima

Description: 卷积码是一种重要的前向纠错信道编码方式，其纠错性能常常优于分组码，且(2,1,7)卷积码已应用于现代卫星通信系统中。Viterbi译码算法能最大限度地发挥卷积码的优异性能。这里采用Verilog  HDL语言设计出(2,1,7)卷积码的编码器模块和基于Viterbi算法的译码器模块，译码器采用全并行结构，译码速度快-Convolutional code is an important forward error correction channel coding method, and its error correction performance is often better than the block code, and (2,1,7) convolutional code has been used in modern satellite communication system. Viterbi decoding algorithm can maximize the performance of convolutional codes. Here is the Verilog HDL design (2,1,7) convolutional code encoder module and decoder module based on Viterbi algorithm, the decoder is designed using the parallel structure and the decoding speed is fast.
Platform: | Size: 10240 | Author: 邓博于、 | Hits:

CodeBus www.codebus.net