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[Other] 三人表决器（三种不同的描述方式）

Description: 用VHDL语言编写的三人表决器，多数服从少数，或者一致通过。-VHDL prepared by the three voting machines, most of the views of the minority, or adopted unanimously.
Platform: | Size: 1024 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] VoteMa

Description: 投票器。这个好像是3人投票器，可以用来做5人的吧~也是以前我们实验的时候用过的。仿真和下载都很顺利。-The voting device. This seems to be 3 people to vote, and can be used to make 5 of it ~ is also the past, we used the experimental time. Simulation and downloading has gone smoothly.
Platform: | Size: 68608 | Author: catalina | Hits:

[VHDL-FPGA-Verilog] vote7-2

Description: 七人表决器 在表决的过程中 多于四个通过 少于四个不通过-Seven people vote in the voting process more than four does not pass through the less than four
Platform: | Size: 1024 | Author: duzhifu | Hits:

[VHDL-FPGA-Verilog] voterandcounter

Description: 用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
Platform: | Size: 2048 | Author: 韩笑 | Hits:

[VHDL-FPGA-Verilog] seven

Description: 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full adder mapping method in order to achieve a vote of seven functions, with the network on any other A seven-member voting machine source code must not identical.
Platform: | Size: 84992 | Author: daisichong | Hits:

[Other] vhdlcodes

Description: with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,electronic voting machine,mod 16 counter,jk flip flop.please accept these codes and make me member of this site.so that i can download code from this site also.i really needed codes please accept that as soon as possible.
Platform: | Size: 2048 | Author: nitin | Hits:

[VHDL-FPGA-Verilog] voter

Description: 用VHDL语言设计三人表决器 新建VHDL设计文件并保存 检查编译 波形仿真 -Design using VHDL language VHDL three new voting system for the design document and save it to check the compiler waveform simulation
Platform: | Size: 33792 | Author: 米石 | Hits:

[VHDL-FPGA-Verilog] biaojueqi

Description: 通过VHDL实现一个三人表决器，两个或者两个以上人投票，择通过，否则，无法通过-VHDL implementation through a three-person voting machines, two or more than two votes, whichever is adopted, otherwise, can not
Platform: | Size: 185344 | Author: 李智 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 一些VHDL的简单实例，包括各种计数器，三人表决器等-Some simple examples of VHDL, including the various counters, three voting machines, etc.
Platform: | Size: 43008 | Author: dxeicho | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 1.7段数码译码器 2.4人表决器 3.8421码十进制计数器 4.9秒减计数器-1.7 Section 2.4 digital decoder person voting 3.8421 yards in 4.9 seconds by a decimal counter counter
Platform: | Size: 8192 | Author: 99 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 这是关于VHDL的五个简单程序，跑马灯、简单时钟、4*4键盘、计价器、7人表决器。-This is about the five simple VHDL program, marquees, a simple clock, 4* 4 keyboard, the meter, 7 voting machine.
Platform: | Size: 5120 | Author: qq | Hits:

[VHDL-FPGA-Verilog] biaojue

Description: VHDL编写的七人表决器，有做课程设计的有福了-Written in VHDL seven voting machine, there are so blessed Oh curriculum design
Platform: | Size: 208896 | Author: 龙刚 | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。 一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。 二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] The.design.of.the.voting.machine

Description: 表决器的设计 设计一个三人的表决器，其中有二人以上同意则投票通过。演示结合实验箱上A区、J区的LED及按键。工作过程如下：带锁的按键按下时，按键上的灯亮表示投票同意；按键松开时，灯熄灭表示投票反对；SW1-SW3这三个按键是3人的投票键，L1灯亮表示投票通过，且蜂鸣器响；L1灯熄灭表示投票未通过，且蜂鸣器不响。利用原理图和VHDL编程相结合的方法来实现-The design of the voting machine
Platform: | Size: 35840 | Author: duopk | Hits:

[VHDL-FPGA-Verilog] voting

Description: 7人表决VHDL程序设计，，表决的原则是输入“1”代表同意，“0”代表不同意，当同意的人数大等于4人时电路输出为“1”，否则为“0”。 ①用VHDL语言写出完整的程序。 -7 voting VHDL programming
Platform: | Size: 11264 | Author: 风 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 七人表决器，可以用于七人表决，很实用，很好,-Seven voting machines, you can vote for seven people, very practical, very good,
Platform: | Size: 73728 | Author: www | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 三人表决器（三种不同的描述方式）以及通用寄存器-Three voting machine (a description of three different ways), and general-purpose registers
Platform: | Size: 2048 | Author: Jason | Hits:

[VHDL-FPGA-Verilog] CPLD-Three-voting

Description: CPLD/FPGA 设计实例手册 用VHDL语言设计三人表决器 用原理图输入的方式设计三人表决器 用verilog-HDL语言设计三人表决器-CPLD/FPGA design example manual Three of the voting machine VHDL language Schematic design of a three-member voting Verilog-HDL language design three-member voting
Platform: | Size: 2754560 | Author: 叶子 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 表决器 奇校验器 3位比较器 4选1 数据选择器-The odd parity voting 3 comparator election of a data selector
Platform: | Size: 412672 | Author: dula | Hits:

[VHDL-FPGA-Verilog] VHDL-design-seven-people-voting

Description: 1、 熟悉VHDL的编程。 2、 熟悉七人表决器的工作原理。 3、 进一步了解实验系统的硬件结构。 -1, familiar with VHDL programming. 2, familiar with the seven voting machine works. 3, to further understand the experimental system hardware architecture.
Platform: | Size: 1147904 | Author: 于治成 | Hits:
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