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Description: Wishbone dma ip core
Platform: |
Size: 7081 |
Author: liwen |
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Description: Wishbone dma ip core
Platform: |
Size: 7168 |
Author: liwen |
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Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.
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Size: 410624 |
Author: Arun |
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Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: |
Size: 32768 |
Author: 孙喆 |
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Description: wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发-dma controller with wishbone interface，fitting for soc design，especially for video development.
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Size: 143360 |
Author: 刘月 |
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Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: |
Size: 2271232 |
Author: 张亚群 |
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Description: 这是一个简单IP核的DMA桥，他有两个WISHBONE接口，该平台可实现在两个相同或不同接口之间DMA数据的搬运。-This is a simple DMA/Bridge IP core. It has two WISHBONE interface. It can perform DMA transfers between the two interfaces or on the same interfaces.
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Size: 143360 |
Author: 云海 |
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Description: 该代码实现了一个基于Wishbone总线协议的DMA控制器，由于SOC可集成的模块越来越多，本文设计的DMAC包含了31个可编程的DMA通道，能够处理多个DMA传输请求。由于数据在Wishbone总线上传输，在总线接口方面，本文设计的DMAC提供了两个既可以作为主机接口又可以作为从机接口的Wishbone接口。当有多个外设同时发出DMA请求时，本文设计的DMAC采用循环优先级和动态优先级相结合的方式，实现了通道仲裁器二级仲裁的功能。为了提高传输效率，本文设计的DMAC不仅支持数据块的传输，还支持高效的分散/集中DMA传输方式。(In this thesis, after in-depth understanding of Wishbone bus protocol and DMA technology, present a design concept of a DMAC integrated into a Wishbone bus based SOC. The DMAC designed in this thesis contains thirty-one programmable DMA channels, which can handle multiple DMA transfer request. As the data is transmitted over the Wishbone bus, the DMAC provides two Wishbone interfaces that can act as a host interface or as a slave interface. When several peripherals issue DMA transfer request at the same time, the DMAC adopts the combination of cyclic priority and dynamic priority to realize the secondary arbitration function of channel arbiter. In order to improve the transmission efficiency, the DMAC not only supports the transmission of data blocks, but also supports efficient scatter/gather DMA transfer mode.)
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Size: 74752 |
Author: Tensor_org |
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