Search - wishbone interface

[VHDL-FPGA-Verilog] wb_conbus.tar

Description: wishbone 源代码，opencore-wishbone source code, opencore
Platform: | Size: 15360 | Author: 姚卫忠 | Hits:

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473088 | Author: Jack | Hits:

[ELanguage] rs232_syscon_v

Description: This a state-machine driven rs232 serial port interface to a "Wishbone" // type of bus.-This a state-driven machine rs232 seria l port interface to a "Wishbone"// type of bus.
Platform: | Size: 11264 | Author: weixing | Hits:

[VHDL-FPGA-Verilog] eth_ocm_80_2

Description: ethernet wishbone interface
Platform: | Size: 208896 | Author: esl | Hits:

[VHDL-FPGA-Verilog] wishbone_VHDL

Description: wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
Platform: | Size: 464896 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] simple_spi.tar

Description: Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
Platform: | Size: 574464 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] pif2wb_latest.tar

Description: This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
Platform: | Size: 2256896 | Author: Arun | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] SDCard_Controller

Description: SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 -SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Platform: | Size: 24576 | Author: xiafei | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[Graph program] wb_dma

Description: wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发-dma controller with wishbone interface，fitting for soc design，especially for video development.
Platform: | Size: 143360 | Author: 刘月 | Hits:

[Internet-Network] ethmac_latest[1].tar

Description: 10M/100M 以太网mac，wishbone接口，可以直接使用-10M/100M Ethernet mac, wishbone interface, you can directly use
Platform: | Size: 18535424 | Author: 阳光 | Hits:

[Com Port] uart16550

Description: uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
Platform: | Size: 1760256 | Author: CloudZhang | Hits:

[Other] ata_latest.tar

Description: The OCIDEC (OpenCores IDE Controller) is a WISHBONE rev.B2 compliant ATA/ATAPI-5 host implementation. The ATA (AT Attachment) interface, also known as IDE (Integrated Drive Electronics) interface, provides a simple interface to low cost non-volatile memories like hard-disk drives, DVD players, CDROM players/writers, CompactFlash and PC-Card devices.
Platform: | Size: 928768 | Author: Gopi | Hits:

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[VHDL-FPGA-Verilog] wb_conbus.tar

[Com Port] simple_spi

[ELanguage] rs232_syscon_v

[VHDL-FPGA-Verilog] eth_ocm_80_2

[VHDL-FPGA-Verilog] wishbone_VHDL

[VHDL-FPGA-Verilog] simple_spi.tar

[VHDL-FPGA-Verilog] pif2wb_latest.tar

[Video Capture] camera_up

[VHDL-FPGA-Verilog] SDCard_Controller

[Embeded-SCM Develop] pci.tar

[Graph program] wb_dma

[Internet-Network] ethmac_latest[1].tar

[Com Port] uart16550

[Other] ata_latest.tar

[Other] yadmc_latest.tar

[VHDL-FPGA-Verilog] wbspec_b4.pdf

[VHDL-FPGA-Verilog] wb_conmax_latest.tar

[VHDL-FPGA-Verilog] led_driver

[VHDL-FPGA-Verilog] Digipot_wb_interface

[VHDL-FPGA-Verilog] wishbone

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