Search - wishbone verilog

[SCM] Wishbone

Description: wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical description of the text block!
Platform: | Size: 1342464 | Author: | Hits:

[VHDL-FPGA-Verilog] wb_conbus.tar

Description: wishbone 源代码，opencore-wishbone source code, opencore
Platform: | Size: 15360 | Author: 姚卫忠 | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Platform: | Size: 8427520 | Author: heartbeat | Hits:

[Software Engineering] Wishbone_from_opencores

Description: 这个是在ＯＰＥＮＣＯＲＥ上收集的wishbone总线的开发说明和指导，随着电子设计开源ＩＰ的大量应用，wishbone总线也越来越普及。-This is collected in OPENCORE Wishbone bus and guide the development of note, with the electronic design of a large number of open source IP applications, wishbone bus is also becoming increasingly popular.
Platform: | Size: 836608 | Author: 刘庆强 | Hits:

[VHDL-FPGA-Verilog] wb_rtc

Description: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Platform: | Size: 8192 | Author: 姓名 | Hits:

[Embeded-SCM Develop] ahb2wishbone_latest.tar

Description: opencore ahb to wishbone bus verilog code
Platform: | Size: 2662400 | Author: xiantongma | Hits:

[ActiveX/DCOM/ATL] pit_latest.tar

Description: Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
Platform: | Size: 595968 | Author: Arun | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[VHDL-FPGA-Verilog] SPI_Wishbone_Controller

Description: FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware description language to achieve
Platform: | Size: 199680 | Author: deng | Hits:

[VHDL-FPGA-Verilog] wishbone_m4_s8

Description: wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
Platform: | Size: 3072 | Author: mis_hey | Hits:

[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar

Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: | Size: 2271232 | Author: 张亚群 | Hits:

[VHDL-FPGA-Verilog] UART_IP_core_for_wishbone

Description: 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
Platform: | Size: 39936 | Author: 张阳 | Hits:

[VHDL-FPGA-Verilog] ahb2wishbone_latest.tar

Description: AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
Platform: | Size: 10640384 | Author: rex | Hits:

[VHDL-FPGA-Verilog] wb_conmax_latest.tar

Description: WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
Platform: | Size: 654336 | Author: 陶宇 | Hits:

[VHDL-FPGA-Verilog] led_driver

Description: LED display verilog code. to generate clocks and wishbone interface
Platform: | Size: 2048 | Author: r_ansal | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
Platform: | Size: 13312 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] wb_conbus

Description: wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
Platform: | Size: 20480 | Author: 蔡搏 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: PCI/WISHBONE bridge Reference Design-PCI/WISHBONE bridge Reference Design
Platform: | Size: 47104 | Author: | Hits:

[VHDL-FPGA-Verilog] Wishbone

Description: wishbone总线的一些研究，包括一些代码-wishbone verilog
Platform: | Size: 271360 | Author: 浩慧 | Hits:

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