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[VHDL-FPGA-Verilog] xiayuwen

Description: verilogHDL语言学习的相关资料，非常好用，还有夏宇闻的课件学verilog的应该都知道夏老师的-Language Learning verilogHDL relevant information, very easy to use, as well as courseware Xia Xue Wen verilog should all know the summer of teachers
Platform: | Size: 1534976 | Author: kinki | Hits:

[Software Engineering] xiayuwen

Description: 北航夏宇闻老师编写的关于从算法设计到硬线逻辑的实现的文章。-XIA Yu-Wen Beihang teacher reports on the algorithm design to hard-line logic, the realization of the article.
Platform: | Size: 3381248 | Author: juan | Hits:

[Other] xiayuwen.Verilog.Tutorials

Description: 夏宇闻Verilog经典教程.pdf,非常好的资料。-XIA Yu-Wen classic Verilog tutorial. Pdf, very good information.
Platform: | Size: 1326080 | Author: dongjuhua | Hits:

[Other] xiayuwen

Description: 夏宇文老师上课所用的verilog课件书籍，是学习fpga的不可多得的资料。-Xia Yuwen teacher verilog courseware used in class books, learning fpga of rare information.
Platform: | Size: 3412992 | Author: zhaorongjian | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL-xiayuwen

Description: 夏宇闻老师的经典教程，对Verlag语言感兴趣的朋友或初学FPGA的朋友是个不错的教程。-XIA Wen classic tutorial teachers, the language of the Verlag FPGA beginner interested friends or friends is a good tutorial.
Platform: | Size: 12108800 | Author: 徐海龙 | Hits:

[VHDL-FPGA-Verilog] xiayuwen

Description: 本程序是夏宇闻老师的verilog数字系统设计教程中的E2PROM完整程序文件，包括信号产生模块，E2PROM读写模块，E2PROM模拟模块，并且在ＩＳＥ上运行成功，测试正确，modelsim仿真成功-This program is the Xia Yu Wen digital system design tutorial E2PROM complete file, including the signal generation module, E2PROM reader module, E2PROM simulation module, and run successfully on the ISE, the test correctly, modelsim simulation success
Platform: | Size: 50176 | Author: 王建伟 | Hits:

[VHDL-FPGA-Verilog] ppt

Description: Verilog数字系统设计教程（夏宇闻）例题源程序 ppt-Verilog digital system design course (XiaYuwen) sample source program PPT
Platform: | Size: 285696 | Author: 陈权标 | Hits:

[VHDL-FPGA-Verilog] Verilog-xiayuwen-text

Description: Verilog数字系统设计教程（夏宇闻）例题源程序-Verilog digital system design course (XiaYuwen) sample source program
Platform: | Size: 265216 | Author: 陈权标 | Hits:

[VHDL-FPGA-Verilog] Verilog-example-by-xiayuwen

Description: 这本书是夏宇文老师在几年前编写的，非常是和初学者，里面有哦对verilog 的详细讲解-a book write by xiyuwen ,This book provides a detailed explanation of verilog
Platform: | Size: 1366016 | Author: pioneer | Hits:

[VHDL-FPGA-Verilog] VerilogHDL

Description: 非常好的夏宇闻的veilogHDL语言学习资料，非常难得的。-Very good the xiayuwen of verilog HDL of language learning materials, and very rare.
Platform: | Size: 22794240 | Author: 曹爽 | Hits:

[Other] Verilog--by-Xiayuwen

Description: Verilog HDL 语言经典教程 主编 夏雨闻 PDF 文件-Verilog HDL language editor Xia Wen classic tutorial PDF file
Platform: | Size: 1350656 | Author: wxh | Hits:

[Other] Verilog(xiayuwen)

Description: verilog入门经典，新手必看，夏宇闻著，内容丰富且详细，逐层深入-Verilog introduction to the classic, Xinshoubikan, like the summer, content rich and detailed, layer by layer
Platform: | Size: 22802432 | Author: 夏思源 | Hits:

[File Format] Verilog-DATAS-xiayuwen

Description: 3.1 引言 3.2 Verilog HDL基本结构 3.3 数据类型及常量、变量 3.4 运算符及表达式 3.5 语句 3.6 赋值语句和块语句 3.7 条件语句3.8 循环语句 3.9 结构说明语句 3.10 编译预处理语句 3.11 语句的顺序执行与并行执行 3.12 不同抽象级别的Verilog HDL模型 3.13 设计技巧-3.1 Introduction 3.2 Verilog HDL basic structure 3.3 data types and constants, variables, operators and expressions 3.6 assignment statements and conditional statements block statements 3.7 3.8 3.9 loops structure described sequential execution and parallel statements 3.10 3.11 preprocessor statements statements 3.12 execution of different levels of abstraction Verilog HDL model 3.13 design tips
Platform: | Size: 1341440 | Author: fanzzu | Hits:

[Other] SystemVerilog_by_XiaYuwen

Description: Classic System Verilog PPT by XiaYuwen
Platform: | Size: 136192 | Author: fissird | Hits:

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