Search - xilinx 12

[Other resource] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3688067 | Author: fuhao | Hits:

[Patch] ISE12.4 lic

Description: ISE 12.4 license文件
Platform: | Size: 5316 | Author: analog2k4@126.com | Hits:

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3687424 | Author: hawd | Hits:

[VHDL-FPGA-Verilog] ISE_chinese_user_guide

Description: Xilinx—ISE的中文使用说明，写的很简单，但对于入门者很实用。看过市面上很多Xilinx的书，发现很多都是在这本书的基础上稍加改写，。
Platform: | Size: 915456 | Author: joan | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述第2章 Verilog HDL基础与开发平台操作指南第3章 Verilog HDL程序结构第4章 VERILOG HDL语言基本要素第5章面向综合的行为描述语句第6章面向验证和仿真的行为描述语句第7章系统任务和编译预处理语句第8章 VERILOG HDL可综合设计的难点解析第9章高级逻辑设计思想与代码风格第10章可综合状态机开发实例第11章常用逻辑的VERILOG HDL实现第12章 XILINX硬核模块的VERILOG HDL调用第13章串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27825152 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 第1章 EDA设计与Verilog HDL语言概述第2章 Verilog HDL基础与开发平台操作指南第3章 Verilog HDL程序结构第4章 VERILOG HDL语言基本要素第5章面向综合的行为描述语句第6章面向验证和仿真的行为描述语句第7章系统任务和编译预处理语句第8章 VERILOG HDL可综合设计的难点解析第9章高级逻辑设计思想与代码风格第10章可综合状态机开发实例第11章常用逻辑的VERILOG HDL实现第12章 XILINX硬核模块的VERILOG HDL调用第13章串口接口的VERILOG HDL设计-Chapter 1 of the EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 of the basic elements for a comprehensive statement in Chapter 6 describe the behavior of surface and simulation to verify the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 to develop an integrated state machine instance 11 Common logic VERILOG HDL Chapter Chapter 12 XILINX to achieve hard-core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27831296 | Author: lyy | Hits:

[Linux-Unix] mgc_licen(1)

Description: license for ise12.2,最新而且很好用，请放心使用。-license for ise12.2，It s lastest fot ise 12.2,good ease to ues.
Platform: | Size: 387072 | Author: 邵磊 | Hits:

[VHDL-FPGA-Verilog] ADPCMDecoder

Description: ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
Platform: | Size: 2048 | Author: DANIEL PAN | Hits:

[VHDL-FPGA-Verilog] xilinx_ise_12

Description: 最新xilinx_ISE-12.3 version License 扩展名.lic-xilinx_ISE-12.3 version License
Platform: | Size: 5120 | Author: TBR | Hits:

[VHDL-FPGA-Verilog] XilinxISEDesignSuite12.1

Description: Xilinx ISE Design Suite 12.1 cd key
Platform: | Size: 1024 | Author: grs | Hits:

[VHDL-FPGA-Verilog] ddr_100Mhz_2011.03.12

Description: 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the two dcm module.
Platform: | Size: 6132736 | Author: 张元甲 | Hits:

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[Other resource] VHDL-XILINX-EXAMPLE26

[Patch] ISE12.4 lic

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

[VHDL-FPGA-Verilog] ISE_chinese_user_guide

[VHDL-FPGA-Verilog] dds_easy

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] verilog

[Linux-Unix] mgc_licen(1)

[VHDL-FPGA-Verilog] ADPCMDecoder

[VHDL-FPGA-Verilog] xilinx_ise_12

[VHDL-FPGA-Verilog] XilinxISEDesignSuite12.1

[VHDL-FPGA-Verilog] ddr_100Mhz_2011.03.12

[SCM] XILINX-ISE-MODELSIN-SE-Simulation

[VHDL-FPGA-Verilog] xilinx_EDK_lesson_ISE12

[Embeded Linux] Xilinx

[VHDL-FPGA-Verilog] THANHGHIDICH

[Software Engineering] an-FPGA-example-base-Xilinx-ISE-12.4

[Software Engineering] kc705_Schematic_xtp132_rev1_1

[VHDL-FPGA-Verilog] vmodcam-ref-vga-demo-12

[Program doc] Modelsim-Xilinx--ISE

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