Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - xilinx 7.1

Search list

[Software Engineering] VHDL

Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
Platform: | Size: 297984 | Author: 西西 | Hits:

[VHDL-FPGA-Verilog] 8086FPGA

Description: xilinx ise 7.1下 实现sparten3 basys板上基于8086FPGA软核的吃豆子游戏-xilinx ise 7.1 under sparten3 basys board based on soft-core 8086FPGA eating beans games
Platform: | Size: 2360320 | Author: 朱万里 | Hits:

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3687424 | Author: hawd | Hits:

[Other] 7

Description: xilinx EDK工程一例 MicroBlaze 内置USB固件程序-xilinx EDK project MicroBlaze case of built-USB firmware
Platform: | Size: 3152896 | Author: 隔夜凉茶 | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_ISIM_vlog_v92

Description: Xilinx DDR2存储器接口调试代码，主频167Mhz，嵌入了CHIPSCORP代码。-Xilinx DDR2 memory interface debug code, frequency 167Mhz, embedded code CHIPSCORP.
Platform: | Size: 3390464 | Author: king523103@163.com | Hits:

[VHDL-FPGA-Verilog] dualporttst-1_0

Description: xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
Platform: | Size: 195584 | Author: zhang | Hits:

[Documents] QPSK

Description: 提出了一个采用(2,1,7)卷积码+QPSK的中频调制解调方案,并在Xilinx公司的100万 门FPGA芯片上实现了该系统。该系统在信噪比SNR为6dB左右时可实现速率超过1Mbit/s、误码率 小于10-5的数据传输。 -Proposed a use of (2,1,7) convolutional code+ QPSK modulation and demodulation of the IF program, and in Xilinx' s FPGA chip one million on implementation of the system. The system SNR to 6dB signal to noise ratio at about the rate may achieve more than 1Mbit/s, less than 10-5 bit error rate of data transmission.
Platform: | Size: 62464 | Author: 张同星 | Hits:

[VHDL-FPGA-Verilog] 45561564

Description: 典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Platform: | Size: 313344 | Author: 王磊 | Hits:

[VHDL-FPGA-Verilog] microblaze_v7_10e

Description: Xilinx软核microblaze源码(VHDL)版本7.10-microblaze IP core of Xilinx, Edition:7.10
Platform: | Size: 411648 | Author: machenghai | Hits:

[Documents] xilinx

Description: -- Hexadecimal to 7 Segment Decoder for LED Display -- Hexadecimal to 7 Segment Decoder for LED Display--- Hexadecimal to 7 Segment Decoder for LED Display -- Hexadecimal to 7 Segment Decoder for LED Display -- Hexadecimal to 7 Segment Decoder for LED Display
Platform: | Size: 53248 | Author: work | Hits:

[VHDL-FPGA-Verilog] bcd_to_7segmentos

Description: bcd to 7 segments display tested on xboard xilinx, all code developed on vhdl
Platform: | Size: 602112 | Author: carlos | Hits:

[Crack Hack] CRC

Description: CRC校验xilinx器件生成CRC校验verilog文件-CRC perl
Platform: | Size: 5120 | Author: icsong | Hits:

[Other] 7_Series_XPE_14_1

Description: xilinx 7系列 FPGA功耗评估，excel格式，-xilinx 7 fpga xpe
Platform: | Size: 4728832 | Author: pzf | Hits:

[Software Engineering] Xilinx-EDK-tutorial

Description: Xilinx EDK tutorial with working principle using embedded C.
Platform: | Size: 459776 | Author: Kanava Jenni | Hits:

[VHDL-FPGA-Verilog] ac701-pcie-rdf0225-2013.2-c

Description: 赛灵思7系列开发板ac701，PCIE参考设计，VHDL/Verilog，开发环境Vivado-xilinx 7 series design Kit AC701 PCIe reference design. VHDL/Verilog, design environment Vivado
Platform: | Size: 3809280 | Author: 凯一 | Hits:

[Program doc] 7-series-clb-architecture

Description: Xilinx 7系列的详细介绍，包括CLB,MEMORY,时钟管理等，对理解7系列FPGA有很大帮助。-Xilinx 7 series of details, including the CLB, MEMORY, clock management, understanding the 7 series FPGA great help.
Platform: | Size: 6008832 | Author: sw | Hits:

[VHDL-FPGA-Verilog] Xilinx-7

Description: Xilinx 7系列的FPGA资料，初学者必看-Xilinx 7 series FPGA data, beginners must see
Platform: | Size: 5710848 | Author: 蔡菜菜 | Hits:

[VHDL-FPGA-Verilog] Vivado 2016.1 安装流程

Description: Vivado是 Xilinx新一代针对7系列及后续 系列及后续 FPGA 的开发平台。 Vivado 2016.1是官方首个支持 是官方首个支持 win10的版本。(Vivado is the new generation of Xilinx for the 7 and subsequent series and subsequent FPGA development platform. Vivado 2016.1 is the official first support, is the official version of the first support win10.)
Platform: | Size: 614400 | Author: 两棵小树 | Hits:

[Other] 7-series-product-selection-guide

Description: xilinx 7-series-product-selection-guide
Platform: | Size: 620544 | Author: johnx0mail0ustc | Hits:

[Other] 02Kintex修炼秘籍-MIG DDR应用3缓存设计

Description: vivado下的MIG教程,适用于XILINX 7系列FPGA(MIG tutorial under vivado.)
Platform: | Size: 4861952 | Author: 城北的D1B | Hits:
« 12 3 4 5 »

CodeBus www.codebus.net