Search - xilinx ddr

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[OS Develop] jsjktbg1_mydown0315 DL : 0: xilinx ddr controler
Update : 2008-10-13 Size : 11.48kb Publisher : lanse
[VHDL-FPGA-Verilog] Xilinx spartan 6 DDR 测试源代码 DL : 1: Xilinx FPGA Spartan 6 上可运行的软核microblaze以及外设DDR, SPI,UART等测试代码
Update : 2011-09-22 Size : 17.62mb Publisher : jameszhou9019
[VHDL-FPGA-Verilog] ddr_verilog_xilinx DL : 0: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Update : 2025-02-17 Size : 128kb Publisher : 陈旭
[VHDL-FPGA-Verilog] ddr_verilog_xilinx DL : 0: 该程序是在xilinx的FPGA上实现DDR_SDRAM接口，程序是用verylog语言写的-that the procedure was in Xilinx FPGA to achieve DDR_SDRAM interface, procedures used to write the language verylog
Update : 2025-02-17 Size : 23kb Publisher : 冯伟
[VHDL-FPGA-Verilog] xapp935 DL : 0: ddr2 controller, verilog source code from xilinx
Update : 2025-02-17 Size : 339kb Publisher : Hubert
[OS Develop] jsjktbg1_mydown0315 DL : 0: xilinx ddr controler
Update : 2025-02-17 Size : 11kb Publisher : lanse
[VHDL-FPGA-Verilog] xapp858 DL : 0: xilinx公司的ＤＤＲ实现源码，希望对你的开发有所帮助-Xilinx DDR to achieve the company s source code, and they hope to be helpful to your development
Update : 2025-02-17 Size : 63kb Publisher : feng
[VHDL-FPGA-Verilog] cntl_ddr3(xilinx) DL : 0: xilinx ddr3最新VHDL代码,通过调试-xilinx ddr3 latest VHDL code through debugging
Update : 2025-02-17 Size : 99kb Publisher : zhang chi
[SCM] DDR_SDRAM_DesignSummarize DL : 0: 基于Xilinx Spartan系列开发板的DDR SDRAM设计方案及经验总结!-Based on the Xilinx Spartan family of development boards and the DDR SDRAM design experience!
Update : 2025-02-17 Size : 331kb Publisher : 曾娟丽
[VHDL-FPGA-Verilog] Xil3S500E_Serial_Flash_v81 DL : 0: 这是一个利用xilinx的macroblaze将用户程序由flash读取至ddr内存的例程，关键是bootloader的写法。-This is a use of Xilinx macroblaze the user program will read from flash memory to ddr routine, the key is the wording of bootloader.
Update : 2025-02-17 Size : 1.27mb Publisher : weichengguanzhe
[VHDL-FPGA-Verilog] 03.EDK8.2 DL : 0: 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests
Update : 2025-02-17 Size : 21.76mb Publisher : 肖姗姗
[VHDL-FPGA-Verilog] ddr_verilog_xilinx DL : 0: xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
Update : 2025-02-17 Size : 663kb Publisher : liujie
[VHDL-FPGA-Verilog] c_xapp260 DL : 0: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Update : 2025-02-17 Size : 1.07mb Publisher : 陈阳
[VHDL-FPGA-Verilog] c_xapp858 DL : 0: 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the interface used to achieve high-performance DDR2 SDRAM controller and data acquisition technology. This data collection technique used in each Virtex ™ -5 I/O has an input serializer/deserializer (ISERDES) and output double data rate (ODDR) function.
Update : 2025-02-17 Size : 437kb Publisher : 陈阳
[VHDL-FPGA-Verilog] c_xapp851 DL : 1: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Update : 2025-02-17 Size : 399kb Publisher : 陈阳
[VHDL-FPGA-Verilog] ddr_verilog_xilinx DL : 0: xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
Update : 2025-02-17 Size : 665kb Publisher : suyufeng
[VHDL-FPGA-Verilog] ddr_sdr_V1_1 DL : 0: DDR控制器 - 用XILINX Virtex II FPGA实现 - 使用DDR MT46V16M16作为仿真模型 - 通用化-DR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device
Update : 2025-02-17 Size : 37kb Publisher : jordanliang
[VHDL-FPGA-Verilog] XAPP200_ddr_sdram_64b DL : 0: Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
Update : 2025-02-17 Size : 1.55mb Publisher : jc
[VHDL-FPGA-Verilog] xst_vlog_bl2cl25 DL : 0: DDR 原厂IP核开源代码控制器vrilogHDL代码(xilinx ddr control xst)
Update : 2025-02-17 Size : 215kb Publisher : happy2050
[Other] 02Kintex修炼秘籍-MIG DDR应用3缓存设计 DL : 0: vivado下的MIG教程,适用于XILINX 7系列FPGA(MIG tutorial under vivado.)
Update : 2025-02-17 Size : 4.64mb Publisher : 城北的D1B

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