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[VHDL-FPGA-Verilog] pwm

Description:
Platform: | Size: 214016 | Author: 熊辉波 | Hits:

[VHDL-FPGA-Verilog] pic16f84

Description: pic MCU的HDL语言代码，实现器件是Xilinx FPGA,经过验证和测试-pic MCU HDL code, is the realization of Xilinx FPGA devices. After testing and validation
Platform: | Size: 48128 | Author: 钟方 | Hits:

[VHDL-FPGA-Verilog] opb_ps2_dual_ref_v1_00_a

Description: 基于Xilinx FPGA实现PS2键盘鼠标接口。版本1.0-Based on Xilinx FPGA realize PS2 keyboard and mouse interface. Version 1.0
Platform: | Size: 16384 | Author: 张力 | Hits:

[Other] XC3S500EPQ208

Description: Xilinx SPARTAN3E design guide line
Platform: | Size: 26624 | Author: 凌峰 | Hits:

[SCM] PBLCD

Description: FPGA 基于PICOBLAZE内核的LCD显示程序,完整,XILINX-PicoBlaze core FPGA-based LCD display program, complete, XILINX
Platform: | Size: 634880 | Author: 鲍纯贝 | Hits:

[Embeded-SCM Develop] high-speed-serialIO

Description: 高速串行IO方面的一本电子书，是xilinx公司发布的，认为相当不错，供大家一起学习-High-speed serial IO aspects of an e-book is issued by Xilinx Inc., consider pretty good for everyone to learn
Platform: | Size: 1708032 | Author: cao | Hits:

[VHDL-FPGA-Verilog] ECCgenAndLoc

Description: 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder location for the ECC error procedures.
Platform: | Size: 1504256 | Author: 卓智海 | Hits:

[VxWorks] vxworks5_5

Description: Xilinx FPGA的PPC的VxWorks开发向导-Xilinx FPGA development of PPC
Platform: | Size: 323584 | Author: 蓝天 | Hits:

[Embeded-SCM Develop] edk_ctt

Description: xiinx的edk开发的文档，看了这个文档，你可以找到所有xilinx EDK开发的相关文档。-xilinx edk development document,ISE10
Platform: | Size: 1005568 | Author: max | Hits:

[Editor] tcon

Description: 资料TW8816的资料，还有一些其他的PDF文档-ziliao
Platform: | Size: 334848 | Author: 李方 | Hits:

[VHDL-FPGA-Verilog] LTC2624_TEST_OK

Description: 以简单的三角波来测试dac芯片LTC2426的功能是否正常.使用的开发板是Xilinx XC3S200AN,使用芯片的转化通道CHO,最后的输出结果为Vp-p大概为3.3V的三角波(Vp-p的大小由参考电压所决定)-A simple triangle wave dac chip to test whether the normal function of the LTC2426. The use of the development board is the Xilinx XC3S200AN, use the chips into channel CHO, the final output Vp-p for about 3.3V triangular wave (Vp-p size from determined by reference voltage)
Platform: | Size: 2199552 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] xilinx_doc

Description: 一本介绍如何使用xilinx的好书，分享给大家-Describes how to use a xilinx books, share to everybody
Platform: | Size: 6767616 | Author: wyq | Hits:

[VHDL-FPGA-Verilog] ddr2

Description: 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Platform: | Size: 2793472 | Author: Zhao Bill | Hits:

[VHDL-FPGA-Verilog] c_xapp454

Description: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Platform: | Size: 217088 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] c_xapp851

Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Platform: | Size: 408576 | Author: 陈阳 | Hits:

[Books] Block_Memory_Generator_v3.3

Description: Xilinx IP core 生成手册-Block_Memory_Generator
Platform: | Size: 1935360 | Author: wang pu | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述第2章 Verilog HDL基础与开发平台操作指南第3章 Verilog HDL程序结构第4章 VERILOG HDL语言基本要素第5章面向综合的行为描述语句第6章面向验证和仿真的行为描述语句第7章系统任务和编译预处理语句第8章 VERILOG HDL可综合设计的难点解析第9章高级逻辑设计思想与代码风格第10章可综合状态机开发实例第11章常用逻辑的VERILOG HDL实现第12章 XILINX硬核模块的VERILOG HDL调用第13章串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27825152 | Author: lyy | Hits:

[Other] XILINX-P-FPGA-

Description: 本书基于 XILINX 的嵌入式开发平台，讲解了嵌入式系统的基本概念；FPGA 原理和 MicroBlaze 处理器和最新的多端口内存控制器（MPMC）。以基于 3 个不同总线和接口的试验，详细讲述了怎样开发用户自定义 IP。 -XILINX book is based embedded development platform, explain the basic concepts of embedded systems FPGA principles and MicroBlaze processor and the latest multi-port memory controller (MPMC). With three different bus and interface-based assays, a detailed account of how to develop a user-defined IP.
Platform: | Size: 6791168 | Author: 张春竹 | Hits:

[Open-source hardware] dwt

Description: Running: C:\Xilinx_Installed\14.3\ISE_DS\ISE\bin\nt\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe -prj G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_beh.prj work.top_dwt work.glbl ISim P.40xd (signature 0x8ef4fb42) Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 Determining compilation order of HDL files
Platform: | Size: 3072 | Author: farrokh | Hits:

[Embeded-SCM Develop] dwt2d

Description: secureip -o G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe -prj G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_beh.prj work.top_dwt work.glbl ISim P.40xd (signature 0x8ef4fb42) Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 Determining compilation order of HDL files
Platform: | Size: 2048 | Author: farrokh | Hits:

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