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[VHDL-FPGA-Verilog] lab1

Description: xilinx sopc技术实例，请多多指教。一个很小的代码-xilinx sopc technical examples, please exhibitions. A very small code
Platform: | Size: 73728 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] example

Description: 几个基本的VHDL例子，包括VGA显示，鼠标键盘PS2接口，数码管等。在XILINX板子上均可运行-Several basic VHDL examples, including VGA display, mouse, PS2 keyboard interface, digital tubes, and so on. XILINX board may be in the running
Platform: | Size: 2675712 | Author: kljlj | Hits:

[VHDL-FPGA-Verilog] petalogic

Description: 这个是一个基于Xilinx FPGA的微控制器软和microblaze移植uclinux的说明文档。由于这些文件都是以网页的形式存在的，所以我下来组织成了电子书的格式，方便大家查看。并且希望对那些希望在FPGA上做嵌入式开发的人有所帮助。还有，上面的东西都是从petalogic的网站上下载的，版权归petalogic所有，我只是把它介绍给大家。-This is a Xilinx FPGA-based soft MCU microblaze documentation of uclinux transplantation. As a result of these documents are in the form of web pages, so I left the organization has become the e-book format, to facilitate view. And hope for those who want to do FPGA Embedded help people. Also, things are from above petalogic download site, copyright petalogic all, I just introduced it to you.
Platform: | Size: 4172800 | Author: 古月 | Hits:

[matlab] XILINX

Description: not so good BPSK software matlab
Platform: | Size: 181248 | Author: mireiacolina | Hits:

[Other] modelsim_xilinx_simulation

Description: xilinx开发环境中应用modelsim se仿真时库文件的建立，包括unisim库-xilinx application development environment, modelsim se the establishment of the simulation library files, including the library, and so unisim
Platform: | Size: 1785856 | Author: Trevor | Hits:

[VHDL-FPGA-Verilog] FPGA_DSP_using_matlab

Description: 这是一个使用matlab语言来实现FPGA的DSP算法的例子。主要是针对xilinx的FPGA芯片。这是一种比较新的编程方法，让matlab工程师也能快速的进行硬件编程。-This is a language to use matlab to implement FPGA-DSP algorithm for example. Mainly aimed at xilinx FPGA-chip. This is a relatively new programming method, so that engineers can quickly matlab hardware programming.
Platform: | Size: 532480 | Author: Martin | Hits:

[Other] Xilinx_Workshop_FPGA_Digital_System_Design_Primer(

Description: 本课程主要内容来自Xilinx全球大学计划Professor Workshops英文版和Xilinx其它相关技术材料。Xilinx公司是世界可编程逻辑器件设计、生产和开发技术的领导者，拥有最先进的可编程逻辑器件产品和完整的技术解决方案。• 一些内容来自各种FPGA技术书籍和技术论坛，它们的作者拥有丰富的理论知识和设计经验，使我受益匪浅-Main content of this course from the Xilinx University Program Professor Workshops worldwide in English and Xilinx other relevant technical materials. Xilinx is the world' s programmable logic device design, production and development of technology leader and the most advanced programmable logic products and a complete technology solutions. • Some of the content from a variety of FPGA technology, books and technology forum, their authors have a wealth of theoretical knowledge and design experience, so I benefited from
Platform: | Size: 5781504 | Author: sam | Hits:

[USB develop] xapp997

Description: xapp997 from xilinx, not so easy to find: an USB application for the Logicore USB core
Platform: | Size: 1699840 | Author: bugidan | Hits:

[USB develop] xapp925

Description: xapp925 from xilinx website, not so easy to download: other USB application for the Cypress chip
Platform: | Size: 2883584 | Author: bugidan | Hits:

[VHDL-FPGA-Verilog] XC4VLX60MB_Lab5_PROM_ISE91

Description: XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is continuously recordable BIT file to the FPGA, you can verify the results, such as Lab1 ~ Lab4 are conducted in this manner, the design. But in the end, if required to maintain the final version of the file, you need to first convert through BIT MCS file, then burn the file records to the PROM MCS inside, after the burn is complete, FPGA can set the M0, M1, M2 s pick Pin 000 (ie Mater Slave Mode), so off power after the next boot, FPGA from the PROM auto-complete Confogurtion, In order to keep this file can be permanent.-XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG' s DOWNLOAD CABLE with the IMPACT software is continuously recordable BIT file to the FPGA, you can verify the results, such as Lab1 ~ Lab4 are conducted in this manner, the design. But in the end, if required to maintain the final version of the file, you need to first convert through BIT MCS file, then burn the file records to the PROM MCS inside, after the burn is complete, FPGA can set the M0, M1, M2' s pick Pin 000 (ie Mater Slave Mode), so off power after the next boot, FPGA from the PROM auto-complete Confogurtion , In order to keep this file can be permanent.
Platform: | Size: 794624 | Author: vkiy | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] Timing_constraints(Xilinx)

Description: 详细介绍FPGA的时序逻辑设计，简要介绍时序设置需要注意的要点与重点，set up time and hold time and so on -Details of the timing of FPGA logic design, timing set to note briefly the main points and key, set up time and hold time and so on
Platform: | Size: 800768 | Author: | Hits:

[VHDL-FPGA-Verilog] XILINX-JTAG-PROGRAMER

Description: Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPGAs are so flexible and reconfigurable that they are capable of massively parallel operations, explicitly tailored to the problem at hand. There are lot of paradigms to put FPGAs at work in a high performance computing environment There are number of limitations which restrict FPGAs to reach the performance of Application Specific Integrated Circuits (ASICs) but they provide the possibility of changing the hardware design easily while outpacing software implementations on general purpose processors.
Platform: | Size: 19456 | Author: javad | Hits:

[Software Engineering] xapp741

Description: xilinx视频处理包示例，包括VDMA，VTC，DDR3控制等。-Xilinx video processing package example, including VDMA VTC, DDR3 control, and so on.
Platform: | Size: 4402176 | Author: sz | Hits:

[Program doc] latch

Description: Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made between of kcm and multiplier. The implementation results show a significant improvement in performance in terms of area, power & timing. In This paper, we propose to design an 8-point FFT using kcm instead of complex multiplier and multiplier. Here our goal is to implement Radix-2 8-point FFT in hardware using hardware language (verilog) here time constraint is measured with the help of Xilinx FPGA (Field Programmable Gate Array).
Platform: | Size: 560128 | Author: Bahu | Hits:

[Other] vivado2014.1-license

Description: xilinx最新软件Vivado2014.1版本的license，安福利FAE提供，绝对好使。-Vivado2014.1 xilinx latest software version license, Avnet FAE offer absolutely so.
Platform: | Size: 1024 | Author: wangbo | Hits:

[VHDL-FPGA-Verilog] T01_UART_CORE

Description: Verilog 实现的 UART串口读写控制核 参数化校验、时钟设置，完整工程（xilinx），包括文档、源码等。供学习参考，希望大家上传自己代码，共同提高，打倒小日本。-Verilog implementation of the UART serial port to read and write control nuclear parametric check, clock setting, complete project (Xilinx), including documentation, source code and so on. For learning reference, hope you upload your own code, improve together, little japanese.
Platform: | Size: 423936 | Author: FEIFEI | Hits:

[VHDL-FPGA-Verilog] Sparten6-CODE-_Verilog

Description: 基于xilinx 厂商的FPGA硬件的开发源代码，包括UART,SPI,以太网通信-The development of FPGA hardware based on xilinx manufacturers source code, including the UART, SPI, Ethernet communication and so on
Platform: | Size: 17125376 | Author: wangxiao | Hits:

[VHDL-FPGA-Verilog] Xilinx的增量编译技术

Description: 增量编译技术，其基本原理就是根据前一次编译的结果，只重新编译部分修改过设计，其它部分则沿用前一次编译的结果，这样就可以缩短总体的编译时间(Incremental compilation technology, the basic principle is based on the results of the previous compilation, only re-editing part of the modified design, the other part is based on the results of the previous compilation, so that you can shorten the overall compile time)
Platform: | Size: 68608 | Author: 小旦 | Hits:

[VHDL-FPGA-Verilog] 好-无线通信FPGA设计-Xilinx

Description: 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless communication FPGA is based on the development platform of Xilinx's FPGA and combines the two directions of FPGA and wireless communication technology. Through a large number of examples of FPGA development, the principle and implementation process of common modules in wireless communication are described in detail, including the basis of digital signal processing, digital filter and multi-rate signal. Processing, digital modulation and demodulation, channel coding, system synchronization, adaptive filtering algorithm, optimal receiver, and key technologies of WCDMA system. The concept of Wireless Communication FPGA Design is clear, and the idea is clear. It pursues comprehensiveness, system and practicality, so that readers can have the ability to develop FPGA in the field of wireless communication in a relatively short time.)
Platform: | Size: 11018240 | Author: 无线电之家99 | Hits:
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