Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - xilinx v

Search list

[Other resource] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit -
Platform: | Size: 359836 | Author: 任学 | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] basys_vga

Description: 一个关于Xilinx的Basys的VGA的工程原码 . 比较完整 .-Xilinx
Platform: | Size: 764928 | Author: | Hits:

[VHDL-FPGA-Verilog] HC164

Description: 用verilog写的HC164的驱动程序，参考了Xilinx的经典算法，做了一点改进~~~很通用，是初学verilog以及FPGA开发很有用的一个程序！
Platform: | Size: 3072 | Author: 屠宁杰 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库 第二章 调用Xilinx CORE-Generator 第三章 使用Synplify.Pro综合HDL和内核 第四章 综合后的项目执行 第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Platform: | Size: 218112 | Author: 青岚之风 | Hits:

[MPI] v2_fifo_vhd_258

Description: 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。-This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Platform: | Size: 92160 | Author: muerqing | Hits:

[VHDL-FPGA-Verilog] I2CController

Description: Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx
Platform: | Size: 22528 | Author: iversn | Hits:

[Other Embeded program] lab6

Description: 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验6系统验证与调试-Xilinx-XUPV2P-based development platform for embedded systems experimental routines: 6 experimental system to verify and debug
Platform: | Size: 7863296 | Author: | Hits:

[Other Embeded program] Face_Detect

Description: Xilinx ISE&EDK 8.2平台的人脸检测系统设计-Xilinx ISE
Platform: | Size: 284672 | Author: huosijia | Hits:

[VHDL-FPGA-Verilog] xilnx_sata

Description: xilinx 的sata解决方案，已对其中内容作了修改，可实现综合-sata the xilinx solutions have been made to amend the contents of which can be used
Platform: | Size: 65536 | Author: 张峰 | Hits:

[VHDL-FPGA-Verilog] xapp460

Description: xilinx hdmi tx rx verilog code
Platform: | Size: 94208 | Author: xiantongma | Hits:

[VHDL-FPGA-Verilog] xapp856

Description: 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
Platform: | Size: 556032 | Author: wicky | Hits:

[Other] sdr_sdram_control

Description: 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
Platform: | Size: 162816 | Author: 李丽 | Hits:

[Software Engineering] ppl

Description: 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programming,
Platform: | Size: 19456 | Author: 生活的 | Hits:

[Books] Xilinx_vga_games_design

Description: 介绍利用XILINX spartan-3e 开发平台开发俄罗斯方块游戏，语言为VHDL-Introduced using XILINX spartan-3e Tetris game development platform, language VHDL
Platform: | Size: 197632 | Author: 张先生 | Hits:

[VHDL-FPGA-Verilog] altpcie_64b_x8_pipen1b

Description: PCIE的软核程序，基于Verilog HDL语言，应用于FPGA的高级编程应用中。-PCIE soft nuclear program, based on Verilog HDL language, used in high-level FPGA programming applications.
Platform: | Size: 357376 | Author: yukai | Hits:

[VHDL-FPGA-Verilog] Example-2-1

Description: XILINX ISE9.X设计指南 第二章-XILINX ISE9.X Design Guide Chapter
Platform: | Size: 515072 | Author: wanglijia | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] ycbcr.v

Description: full pipelined RGB->YUV 420 converter, Xilinx/Altera implementable
Platform: | Size: 13312 | Author: LANC.DEV | Hits:

[VHDL-FPGA-Verilog] V-6-FPGA-Configure-Guide

Description: Xilinx公司的Virtex-6配置指南，是详细的官方指南-Virtex-6 configuration guide Xilinx company, is the official guide
Platform: | Size: 2055168 | Author: fxx | Hits:
« 12 »

CodeBus www.codebus.net