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[
VHDL-FPGA-Verilog
]
xapp856
Description:
基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
Platform:
|
Size:
556032
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Author:
wicky
|
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Search - xilinx.com SDR_4TO1_16CHAN_RX.v
Search - xilinx.com SDR_4TO1_16CHAN_RX.v