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Embeded-SCM Develop List Page 166

[ARM-PowerPC-ColdFire-MIPSSTM32 brushed motor controller

Description: STM motor controll. Brushed DC motor current controller. Based on stm32f103 controller.
Platform: | Size: 7713513 | Author: bokic8 | Hits:

[Embeded-SCM Develop用DSP2812开发的无刷直流电机控制程序

Description: The relevant program of brushless motor control development with DSP 2812.
Platform: | Size: 308224 | Author: lini013 | Hits:

[SCMSTM777_eMMC

Description: STM32F777 drives eMMC card, passes the pro-test, and can add file system.
Platform: | Size: 11227136 | Author: 地质王磊 | Hits:

[VHDL-FPGA-VerilogPID_Verilog

Description: The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.
Platform: | Size: 1024 | Author: wrnd | Hits:

[Embeded-SCM DevelopFirmware_F405 V1.2.1

Description: Hardware resources: 1, MCU: STM32F405RGT6 (FLAH: 1024K, RAM: 196K, system running clock frequency: 168MHz) 2, IMU: MPU6000 (communication mode: SPI1, SCK: PA5 MISO: PA6 MOSI: PA7 CS: PC2) 3, barometer: BMP280 (communicat
Platform: | Size: 1748992 | Author: wjr111 | Hits:

[Embeded-SCM Develop路灯控制器

Description: Familiar with the software and hardware environment, C language and debugging mode of CodeWarrior embedded development system, master its usage and debugging mode, will establish and design a larger project containing mo
Platform: | Size: 287744 | Author: Enfin | Hits:

[SCMSTM32空工程

Description: STM32F103 standard library engineering code, has completed the addition of various documents, the main function and interrupt a blank, change the chip model can start to write their own code for the start of a new projec
Platform: | Size: 4116480 | Author: 芝麻团子 | Hits:

[VHDL-FPGA-VerilogE7_3

Description: The adaptive equalizer based on the symbol LMS algorithm is simulated. The performance simulation of the algorithm is required, the input signal for FPGA test is generated, and the data range of simulation weight in the
Platform: | Size: 950272 | Author: SEXYLADY | Hits:

[VHDL-FPGA-Verilog滤波器实验报告

Description: Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, an
Platform: | Size: 342016 | Author: 羊羊驼 | Hits:

[VHDL-FPGA-Verilog哈夫曼编码器设计实验报告

Description: Design a 1MHz FIR low pass filter. Huffman coding is required for a section of data sequence to make the average code length the shortest, and the output of each element encoding and the encoded data sequence. The elemen
Platform: | Size: 182272 | Author: 羊羊驼 | Hits:

[SCMLT8920 Tx+Rx Demo

Description: Using Arduino board to realize LT8920 wireless transceiver, IO port should be modified according to its configuration, and "loop*" should be changed to send or receive according to need.
Platform: | Size: 3072 | Author: Zheng Nick | Hits:

[SCMADS1118_2

Description: STM32F103--->ADS1118
Platform: | Size: 3376128 | Author: zybo | Hits:

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