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状态机
Downloaded:0
This code implements a finite state machine with the state transition graph through verilog.
Update
: 2025-01-09
Size
: 180kb
Publisher
:
yuguofang
遥控器编码电路
Downloaded:0
The code according to the timing diagram, using Verilog code to achieve the function of the encoding circuit of the remote controller.
Update
: 2025-01-09
Size
: 127kb
Publisher
:
yuguofang
遥控器接收解码电路
Downloaded:6
Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit
Update
: 2025-01-09
Size
: 168kb
Publisher
:
yuguofang
dds1
Downloaded:0
DDS outputs a sine wave to control frequency by modifying the frequency control word
Update
: 2025-01-09
Size
: 5.31mb
Publisher
:
明月惊心
PLX_SDK_v7_11_Final_2014-03-04
Downloaded:0
PLX Latest PCI Development Kit 2014-03-04 The latest version
Update
: 2025-01-09
Size
: 75.71mb
Publisher
:
leguldrdu
vivado_license_2016.4
Downloaded:0
vivado 2016.4 license
Update
: 2025-01-09
Size
: 1kb
Publisher
:
wowoqiang
dot_matrix
Downloaded:0
The digital tube is from one to nine
Update
: 2025-01-09
Size
: 459kb
Publisher
:
nbca
spi_master
Downloaded:0
Master slave mode of SPI communication
Update
: 2025-01-09
Size
: 4.97mb
Publisher
:
karviezz
code_cover_on_black_level_test_project1
Downloaded:0
The TB for the code coverage test of the video processing black level correction module
Update
: 2025-01-09
Size
: 89kb
Publisher
:
莫勒
工作簿1
Downloaded:0
Just hole teacher talk, so that six new development of the party, you find a time, with the volunteer book, together to find the blue Secretary talk, @ Wang Kuo, you're responsible for this thing, a common time to go, go
Update
: 2025-01-09
Size
: 15kb
Publisher
:
徐礼维
cpu_vhdl_vivado
Downloaded:0
A basic CPU demo on the FPGA platform...
Update
: 2025-01-09
Size
: 1.2mb
Publisher
:
deadstar
oneMHZ
Downloaded:0
20Mhz frequency divider
Update
: 2025-01-09
Size
: 187kb
Publisher
:
zuys
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4311
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