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VHDL-FPGA-Verilog list
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a detailed guide of Quartus II
Update : 2025-01-10 Size : 516kb Publisher : miyoujia

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sequence detection with state mation
Update : 2025-01-10 Size : 158kb Publisher : tc280

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FPGA scrambler, scrambler specifications for a 15 bit shift register.
Update : 2025-01-10 Size : 31kb Publisher : 菜菜0106

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UART with Verilog, there are frequency divider module, can adjust the baud rate
Update : 2025-01-10 Size : 10.3mb Publisher : zmxer

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Fast Ethernet communication between FPGA and W5300 chip, the actual project in many applications
Update : 2025-01-10 Size : 4kb Publisher : bug赵

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dac controller ip /dac controller
Update : 2025-01-10 Size : 2kb Publisher : haohmf

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Digital_Tube_Core/Digital_Tube ip
Update : 2025-01-10 Size : 3kb Publisher : haohmf

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uart receive TX_IP_Source
Update : 2025-01-10 Size : 12kb Publisher : haohmf

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uart transmit TX_IP_Source
Update : 2025-01-10 Size : 9kb Publisher : haohmf

A good set of learning information for Verilog timing chapter, with source code and engineering documents, you can follow the tutorial self-study
Update : 2025-01-10 Size : 57.57mb Publisher : UestcCoder

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Digital tube data shift display
Update : 2025-01-10 Size : 203kb Publisher : 稷下

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SRAM configuration OV7620 frame cache
Update : 2025-01-10 Size : 12.61mb Publisher : 寇梓黎
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