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VHDL-FPGA-Verilog list
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chysn
Downloaded:0
Automatic identification in the matlab environment the size of the connected area, For time-frequency analysis algorithm, Principal component analysis of multivariate data analysis projection.
Update
: 2025-01-10
Size
: 147kb
Publisher
:
tfeaivu
sai_ex72
Downloaded:0
This program has exceeded the performance of other algorithms, Including AHP, factor analysis, regression analysis, cluster analysis, DC-DC power single-part set-loop control.
Update
: 2025-01-10
Size
: 147kb
Publisher
:
pqsgpjm
FPGA 经典 100 问
Downloaded:0
FPGA classic 100 questions, some better data collation
Update
: 2025-01-10
Size
: 3.11mb
Publisher
:
刘磊帅锅
cordic
Downloaded:0
verilog version of cordic algorithm
Update
: 2025-01-10
Size
: 4kb
Publisher
:
垚垚佟
jp
Downloaded:0
EDA experiment with Verilog language
Update
: 2025-01-10
Size
: 2kb
Publisher
:
miaomiaojiang
y210
Downloaded:0
EDA experiment with verilog language
Update
: 2025-01-10
Size
: 1kb
Publisher
:
miaomiaojiang
clock1
Downloaded:0
EDA experiment with verilog language
Update
: 2025-01-10
Size
: 1kb
Publisher
:
miaomiaojiang
digital_lock_vga_display
Downloaded:0
Altera DE1 platform digital password lock design, can drive VGA display
Update
: 2025-01-10
Size
: 17.07mb
Publisher
:
SDUGNN
jingxiang_beipin
Downloaded:0
To achieve encoder and 4 times the frequency, can be used for motor speed and so on.
Update
: 2025-01-10
Size
: 4kb
Publisher
:
子炎恋紫雪
keypad
Downloaded:0
4 * 4 of the film button, using the state machine to achieve decoding and key function
Update
: 2025-01-10
Size
: 2mb
Publisher
:
子炎恋紫雪
uart_ip
Downloaded:0
Implementation of serial communication module settings, including frequency division, baud rate generation, interface timing requirements
Update
: 2025-01-10
Size
: 6kb
Publisher
:
子炎恋紫雪
cmos_i2c_ov7670
Downloaded:0
Complete the OV7670 camera an I2C protocol configuration, slave host timing read write function
Update
: 2025-01-10
Size
: 22kb
Publisher
:
子炎恋紫雪
«
1
2
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.49
.50
.51
.52
.53
154
.55
.56
.57
.58
.59
...
4311
»
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