VHDL-FPGA-Verilog List Page 168

VHDL-FPGA-Verilog list

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Altera-verilog-DS1302_ok Downloaded：0: Altera flatform, dirve ds1302 device, test ok.
Update : 2025-01-11 Size : 962kb Publisher : 武哥
Altera-verilog-I2C Downloaded：0: Altera flatform, use verilog code i2c, test ok.
Update : 2025-01-11 Size : 985kb Publisher : 武哥
Altera-verilog-LCD1602 Downloaded：0: use verilog code , driving lcd1602 device, test ok.
Update : 2025-01-11 Size : 929kb Publisher : 武哥
Altera-verilog-LCD12864 Downloaded：0: use altera fpga flatform, verilog language, driving LCD12864 device, test ok.
Update : 2025-01-11 Size : 393kb Publisher : 武哥
Altera-verilog-StepMotor Downloaded：0: on altera fpga flatform, use verilog language, driving stepmotor, and test ok.
Update : 2025-01-11 Size : 300kb Publisher : 武哥
CCS实现FFT Downloaded：0: DSP learning, personal FFT algorithm for implementation, which is a very good code procedure, it is worth learning
Update : 2025-01-11 Size : 3.06mb Publisher : 喜子星
h265enc_v1.0 Downloaded：0: H265 hardware codec (Fudan University)
Update : 2025-01-11 Size : 14.03mb Publisher : Brook_Li
h264enc_v1.0 Downloaded：0: h.264 fpga http://soc.fudan.edu.cn/vip
Update : 2025-01-11 Size : 1.38mb Publisher : shazi_沙子
FM Downloaded：1: Using Verilog, HDL, and FM modulation signals.
Update : 2025-01-11 Size : 1kb Publisher : LCG007
project_2 Downloaded：0: simple gates using ip integrator from xilinx
Update : 2025-01-11 Size : 277kb Publisher : yousif2048
uart Downloaded：0: Serial port to send and receive functions, data processing module can modify its own.
Update : 2025-01-11 Size : 6kb Publisher : Nate777
autoseller Downloaded：0: (1) coins and paper notes can be entered. The range of coin recognition is 5 cents and 1 yuan coins. The range of identification of notes is 1 yuan, 5 yuan, 10 yuan, 20 yuan, 50 yuan, 100 yuan. Money can be put into coin
Update : 2025-01-11 Size : 7.99mb Publisher : johnnewer

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