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VHDL-FPGA-Verilog list
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uarttx
Downloaded:0
Fpga board verilog write serial port to send data module, the main can look at ideas, is also available
Update
: 2025-01-14
Size
: 1kb
Publisher
:
徐林
DSP_XINTF_FPGA
Downloaded:1
Carried out between the DSP and the FPGA XINTF asynchronous communication functions, debugging, and stable operation
Update
: 2025-01-14
Size
: 5.39mb
Publisher
:
刘帅
Example2
Downloaded:0
Based VHDL design Gray Gray code encoder (Gray) code is a reliability of the encoder, it has been widely used in digital systems
Update
: 2025-01-14
Size
: 3kb
Publisher
:
贺泽伟
Example3
Downloaded:0
Including synchronous and asynchronous clear to enable the addition counter binary counter is the most widely used one of the most versatile counter with asynchronous clear and specific work process synchronization enabl
Update
: 2025-01-14
Size
: 3kb
Publisher
:
贺泽伟
Example4
Downloaded:0
Dynamic eight seven-segment LED display circuit design uses two one four, 7-segment LED common learning CASE statement VHDL design methods and the multi-level
Update
: 2025-01-14
Size
: 3kb
Publisher
:
贺泽伟
Example5
Downloaded:0
NC divider d esign feature is that when the given input different input data, the frequency divider with a different frequency division ratio of the input clock signal, the count value NC divider is parallel preset addin
Update
: 2025-01-14
Size
: 3kb
Publisher
:
贺泽伟
paobiao
Downloaded:0
Use verilog to achieve run time function
Update
: 2025-01-14
Size
: 16.32mb
Publisher
:
yang
arinc429_transmitter
Downloaded:2
Simple Arinc-429 transmitter channel description on Verilog HDL with parameterized DATA FIFO.
Update
: 2025-01-14
Size
: 4kb
Publisher
:
scnn86
apb_spi
Downloaded:0
Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
Update
: 2025-01-14
Size
: 11kb
Publisher
:
scnn86
apb_i2c
Downloaded:0
Simple realization of I2C interface on System Verilog HDL with support of interrupt generation.
Update
: 2025-01-14
Size
: 6kb
Publisher
:
scnn86
ahb_ebc
Downloaded:0
Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
Update
: 2025-01-14
Size
: 10kb
Publisher
:
scnn86
timer
Downloaded:0
Simple 32-bit timer realization with APB interface with support of interrupt generation and switching clock source.
Update
: 2025-01-14
Size
: 3kb
Publisher
:
scnn86
«
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.69
.70
.71
.72
.73
274
.75
.76
.77
.78
.79
...
4311
»
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