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VHDL-FPGA-Verilog list
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USART
Downloaded:0
Based on the ARM and FPGA communication experiment of USART
Update
: 2025-03-04
Size
: 1.32mb
Publisher
:
萧砧
w5500_spi_fpga
Downloaded:0
A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address
Update
: 2025-03-04
Size
: 55kb
Publisher
:
nothing
E5_1_AskMod
Downloaded:0
Matlab simulation 2ask and 4ask. Can observe the signal time domain waveform and spectrum.
Update
: 2025-03-04
Size
: 1kb
Publisher
:
杨某人
ASKMod
Downloaded:0
ASK modulation signal verilog VHL design, in ise to achieve the ASK signal modulation and demodulation.
Update
: 2025-03-04
Size
: 1kb
Publisher
:
杨某人
E4_4_IIR4Functions
Downloaded:0
With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
Update
: 2025-03-04
Size
: 1kb
Publisher
:
杨某人
uvm-1.1
Downloaded:0
Learn good about IC verification, including all engineering of UVM-1.1a and UVM-1.1d, for beginners based on the UVM platform for IC verification.
Update
: 2025-03-04
Size
: 6.89mb
Publisher
:
李菲
digital_clock
Downloaded:0
Vivado based on the FPGA digital alarm clock procedures, verilog language
Update
: 2025-03-04
Size
: 3kb
Publisher
:
kan
project_fir_test
Downloaded:0
Verilog based FIR filter design, the use of BASYS3 as a development tool
Update
: 2025-03-04
Size
: 37.35mb
Publisher
:
kan
fft_ex1
Downloaded:0
Verilog based on the FFT design, the use of vivado as a development platform
Update
: 2025-03-04
Size
: 4.37mb
Publisher
:
kan
candy_machine
Downloaded:0
Verilog Code for Candy Machine State Machine
Update
: 2025-03-04
Size
: 470kb
Publisher
:
gotu0000
universal_prescalar
Downloaded:0
Verilog Code for universal prescalar
Update
: 2025-03-04
Size
: 29kb
Publisher
:
gotu0000
priority_decoder
Downloaded:0
Verilog Code for priority decoder
Update
: 2025-03-04
Size
: 461kb
Publisher
:
gotu0000
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