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VHDL-FPGA-Verilog list
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A FIR low-pass filter in the fpga source code, can be used in the communication reference code modulation shaping filter
Update : 2025-01-14 Size : 1kb Publisher : 右下角

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4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
Update : 2025-01-14 Size : 1kb Publisher : 右下角

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DEF algorithm for FIR filter verilog code with multiplier IP core, can be directly used simulation
Update : 2025-01-14 Size : 2kb Publisher : 右下角

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Stepper motor positioning control system VHDL program and simulation
Update : 2025-01-14 Size : 5kb Publisher : Richie_Zen

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Touch screen driver based on 7z010
Update : 2025-01-14 Size : 60.88mb Publisher : johu

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LED driver
Update : 2025-01-14 Size : 3.26mb Publisher : 曹振吉

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U5FEB u901F u5085 u91CC u53F6 u53D8 u6362 u7684verilog u6A21 u5757 uFF0C u7ECF u6D4B u8BD5 u53EF u7528 uFF0C u4E4B u524D u7528 u8FC7 u3002
Update : 2025-01-14 Size : 1kb Publisher : 徐林

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uart communication
Update : 2025-01-14 Size : 250kb Publisher : 曹振吉

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SRAM write and read
Update : 2025-01-14 Size : 81kb Publisher : 曹振吉

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IIC communication
Update : 2025-01-14 Size : 464kb Publisher : cao_sir

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Fast Fourier transform verilog module, the experiment is available, you can get some ideas
Update : 2025-01-14 Size : 2kb Publisher : 徐林

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Udp agreement ipreceive module, written with verilog, the idea is clear
Update : 2025-01-14 Size : 2kb Publisher : 徐林
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