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VHDL-FPGA-Verilog list
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Quartus environment prepared by the FPGA measurement frequency of the program, high measurement accuracy, measuring range 0-10MHZ, the measurement results can be displayed on the digital tube.
Update : 2025-01-15 Size : 6.95mb Publisher : songzhi

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Quartus environment prepared by the FPGA integrated test program, to achieve frequency measurement, digital display, 12864 LCD, 1602 LCD display, dot matrix scan display, AD sampling program, DA output voltage program, y
Update : 2025-01-15 Size : 11.29mb Publisher : songzhi

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sd card testbench
Update : 2025-01-15 Size : 2.07mb Publisher : 马森

cortex m0 mcu system synopsys verilog code
Update : 2025-01-15 Size : 29kb Publisher : 陈显亮

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Uart serial send module, where filter is the key to shake
Update : 2025-01-15 Size : 2.21mb Publisher : bh

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Uart serial port receiving module, the received data string and turn
Update : 2025-01-15 Size : 2.26mb Publisher : bh

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Creation of FPGA-based device. circuit represents a simple device, containing D Flip-Flop with optional asynchronous Reset inputs and AND logic gate
Update : 2025-01-15 Size : 201kb Publisher : Tasko

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memristor based digital to analog converter a prototype model vhdl code
Update : 2025-01-15 Size : 128kb Publisher : divyaramkumar

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this document consists of network on chip simulation screenshots and results
Update : 2025-01-15 Size : 245kb Publisher : divyaramkumar

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this the final project report on VHDL development on noc
Update : 2025-01-15 Size : 798kb Publisher : divyaramkumar

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final sem project report completed one on network on chip data processing
Update : 2025-01-15 Size : 798kb Publisher : divyaramkumar

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OSCFAR the most important sorting algorithm to achieve a single cycle of a set of data after sorting the number of specific serial number, as a reference value of CFAR.
Update : 2025-01-15 Size : 3kb Publisher : wang
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