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VHDL-FPGA-Verilog list
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DDR3 read and write FPGA implementation of the code, the test passed
Update : 2025-01-15 Size : 6.9mb Publisher : tengdaizhou

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driver of the lcd
Update : 2025-01-15 Size : 1kb Publisher : sdk

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100M Ethernet UDP protocol in the FPGA implementation, through the test
Update : 2025-01-15 Size : 8.23mb Publisher : tengdaizhou

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1000M Ethernet UDP protocol in the FPGA to achieve source, the test passed
Update : 2025-01-15 Size : 8.31mb Publisher : tengdaizhou

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OV7670 camera LCD display FPGA code, the test passed
Update : 2025-01-15 Size : 7.82mb Publisher : tengdaizhou

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16-bit addr, 8 bit data I2C master verilog
Update : 2025-01-15 Size : 3kb Publisher :

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CMOS Sensor input module
Update : 2025-01-15 Size : 1kb Publisher :

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EEPROM verilog simulation module
Update : 2025-01-15 Size : 4kb Publisher :

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FPGA output to HDMI Tx module in verilog
Update : 2025-01-15 Size : 14kb Publisher :

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802.1as gptp verilog module, part of EAVB procotol
Update : 2025-01-15 Size : 2kb Publisher :

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use Sram with ring fifo Spartan-3
Update : 2025-01-15 Size : 3.05mb Publisher : lee

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With QuartusII13.0 software, DE1 development board that supports VGA screen realization of table tennis game, while achieving seven-segment LED scoring, ball impact sound, and other functions
Update : 2025-01-15 Size : 6.26mb Publisher : 陈正鑫
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