VHDL-FPGA-Verilog List Page 296

VHDL-FPGA-Verilog list

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huxideng Downloaded：0: With the Quartus software, DE1 development board to achieve the breathing light, Led the first light gradually dimmed, and then gradually brightened by the dark
Update : 2025-01-15 Size : 13.18mb Publisher : 陈正鑫
setmin_sec Downloaded：0: With QuartusII13.0 software, DE1 development board to achieve the clock procedures can be set up time
Update : 2025-01-15 Size : 4.29mb Publisher : 陈正鑫
FPGA_Projects_100 Downloaded：0: FPGA examples
Update : 2025-01-15 Size : 12.81mb Publisher : 张健
DDS Downloaded：0: Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
Update : 2025-01-15 Size : 128kb Publisher : 梁世强
FINAL_CODE_CAM Downloaded：0: this is a VHDL code for content address memory
Update : 2025-01-15 Size : 173kb Publisher : divya
ex_2 Downloaded：0: CS_r[0] < CS CS_r[1] < CS_r[0] wrreq_r[0] < wrreq wrreq_r[1] < wrreq_r[0] READ_sig_old[0] < READ_sig READ_sig_old[1] < READ_sig_old[0]
Update : 2025-01-15 Size : 8kb Publisher : 王亚斌
ppscode Downloaded：0: verilog code, second pulse output for synchronization acquisition
Update : 2025-01-15 Size : 3.12mb Publisher : 华
ADS2807_Ctrl Downloaded：0: ADS2807 control, module function: retrieve control word, control AD sampling rate and AD addre
Update : 2025-01-15 Size : 1kb Publisher : 王亚斌
EMIF Downloaded：0: This is DSP EMIF bus and FPGA communication as an example, has been testing can be used
Update : 2025-01-15 Size : 120kb Publisher : steef
sgmii Downloaded：0: This the development of relevant V5 relevant SGMII routines, are helpful for learning SGMII homecoming
Update : 2025-01-15 Size : 5.44mb Publisher : steef
xapp897 Downloaded：0: Video streaming example VHDL
Update : 2025-01-15 Size : 6.63mb Publisher : Yerba
DE2_115_ControlPanel_V2.2.0 Downloaded：0: This file may be support learn VHDL code
Update : 2025-01-15 Size : 5.05mb Publisher : Phu

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