VHDL-FPGA-Verilog List Page 300

VHDL-FPGA-Verilog list

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AX301 Downloaded：0: 10 in the black gold AX301 development board to achieve the program source program, the program can be burned into the board Included in the word a detailed description of the various engineering functions
Update : 2025-01-15 Size : 59.06mb Publisher : 韩大马
testadcom Downloaded：0: XILINX FPGA XC6SLX9 XC6SLX25
Update : 2025-01-15 Size : 26kb Publisher : 滕奔
Buf_FiFo Downloaded：0: verilog write FIFO, inside the IP core and control module,
Update : 2025-01-15 Size : 5kb Publisher : 王红伟
scrambler Downloaded：0: Verilog prepared by the ADC scrambled program (scrambler) inside with scrambler description, experimental data can be broken up, write their own testbench test
Update : 2025-01-15 Size : 216kb Publisher : 王红伟
Lab-1 Downloaded：0: Design and simulate D flip flop with reset button. Objectives Explore Modelsim through a simple circuit design.
Update : 2025-01-15 Size : 213kb Publisher : Amr
Lab2 Downloaded：0: Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim
Update : 2025-01-15 Size : 607kb Publisher : Amr
Lab3 Downloaded：0: Sequential binary Message detector Objectives 1. Working with finite state machines. 2. Defining user types in VHDL
Update : 2025-01-15 Size : 183kb Publisher : Amr
Lab4 Downloaded：0: RAM design Objectives 1. Working with generic units. 2. Working with Arrays 3. Working with integers
Update : 2025-01-15 Size : 158kb Publisher : Amr
fir25 Downloaded：0: VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit of hardware requirements), which calls the multiplier official API, can be
Update : 2025-01-15 Size : 1kb Publisher : wangjin
fir_csd Downloaded：0: vdhl achieve FIR, multiplier using CSD coding, in the case of resource constraints, can save a lot of resources
Update : 2025-01-15 Size : 3kb Publisher : wangjin
uart_test Downloaded：0: UART IP and test on nios
Update : 2025-01-15 Size : 13.08mb Publisher : wangxin
traffic-light-FPGA Downloaded：0: FPGA do traffic lights at the junction of the complete experiment, the class was up to 95 points, explain in detail, with engineering documents
Update : 2025-01-15 Size : 2.27mb Publisher : anbao

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