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VHDL-FPGA-Verilog list
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Verilog Testbench for 16Bit Group Ripple Adder
Update : 2025-01-16 Size : 29kb Publisher : Raz

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Verilog Module for parity
Update : 2025-01-16 Size : 24kb Publisher : Raz

Verilog Module for a 3 to 8 bit decoder
Update : 2025-01-16 Size : 83kb Publisher : Raz

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Verilog Module for 7-Segment-Display Decoder for Common-Anode LED
Update : 2025-01-16 Size : 235kb Publisher : Raz

Verilog Module for 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
Update : 2025-01-16 Size : 145kb Publisher : Raz

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package for image reading and writing in vhdl
Update : 2025-01-16 Size : 2kb Publisher : kaissallami

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add 2 bits and display result on 7 segment (vhdl)
Update : 2025-01-16 Size : 63kb Publisher : Ridamir

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Based on the ISE14.7, soft-core SOC custom IP core source code, 8 registers, all derived, can be used as FL-FS communication interface, with several other drivers IP core
Update : 2025-01-16 Size : 6.25mb Publisher : 黄均铭

(the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
Update : 2025-01-16 Size : 18.27mb Publisher : Rick007007

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Sopc system implementation with a counter on DE2 platform, the system includes an embedded microprocessor, a JTAG UART and a timer
Update : 2025-01-16 Size : 17.65mb Publisher : 王锋

FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!
Update : 2025-01-16 Size : 2.53mb Publisher : mayuan

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Achieve decoder with verilog language, including reports and experimental data stream file
Update : 2025-01-16 Size : 1.54mb Publisher :
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