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VHDL-FPGA-Verilog list
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16Bit-Group-Ripple-Adder
Downloaded:0
Verilog Testbench for 16Bit Group Ripple Adder
Update
: 2025-01-16
Size
: 29kb
Publisher
:
Raz
BCD-Counter
Downloaded:0
Verilog Module for parity
Update
: 2025-01-16
Size
: 24kb
Publisher
:
Raz
Error-Correcting-For-7bit-Hamming-Code
Downloaded:0
Verilog Module for a 3 to 8 bit decoder
Update
: 2025-01-16
Size
: 83kb
Publisher
:
Raz
Frequency-Meter
Downloaded:0
Verilog Module for 7-Segment-Display Decoder for Common-Anode LED
Update
: 2025-01-16
Size
: 235kb
Publisher
:
Raz
Parallel-To-Serial-Converter
Downloaded:0
Verilog Module for 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
Update
: 2025-01-16
Size
: 145kb
Publisher
:
Raz
pgm
Downloaded:0
package for image reading and writing in vhdl
Update
: 2025-01-16
Size
: 2kb
Publisher
:
kaissallami
Add2bits
Downloaded:0
add 2 bits and display result on 7 segment (vhdl)
Update
: 2025-01-16
Size
: 63kb
Publisher
:
Ridamir
soc_ip-2016-10-12
Downloaded:0
Based on the ISE14.7, soft-core SOC custom IP core source code, 8 registers, all derived, can be used as FL-FS communication interface, with several other drivers IP core
Update
: 2025-01-16
Size
: 6.25mb
Publisher
:
黄均铭
DIGITAL-SIGNAL-PROCESSING-WITH-FPGA
Downloaded:0
(the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
Update
: 2025-01-16
Size
: 18.27mb
Publisher
:
Rick007007
hsu_eda2013am_nios32
Downloaded:0
Sopc system implementation with a counter on DE2 platform, the system includes an embedded microprocessor, a JTAG UART and a timer
Update
: 2025-01-16
Size
: 17.65mb
Publisher
:
王锋
clock-with-alarm-and-timer
Downloaded:0
FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!
Update
: 2025-01-16
Size
: 2.53mb
Publisher
:
mayuan
decoder
Downloaded:0
Achieve decoder with verilog language, including reports and experimental data stream file
Update
: 2025-01-16
Size
: 1.54mb
Publisher
:
李
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