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VHDL-FPGA-Verilog list
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test5
Downloaded:0
The experiment required to complete the task in the role of the clock signal through the input keys displays the corresponding key on the digital tube. In the experiment, the digital clock as scan clock 1KHZ with four to
Update
: 2025-01-16
Size
: 358kb
Publisher
:
小方
test6
Downloaded:0
This experiment is the use of the experimental system of the key switch module and LED modules and digital control module to real Now a simple seven-person voting function. Key switch module in the key 1 ~ key 7 that sev
Update
: 2025-01-16
Size
: 280kb
Publisher
:
小方
Verilog-codes-on-various-logical-functions
Downloaded:0
Useful verilog programs on various logical functions like D Flip-Flop, DSP butterfly unit, Multiplexers, etc.
Update
: 2025-01-16
Size
: 390kb
Publisher
:
Dennis
project1
Downloaded:0
fpga simple little application development projects, for beginners to learn
Update
: 2025-01-16
Size
: 868kb
Publisher
:
mike
project2
Downloaded:0
About verilog finite state machine design, finite state machine for beginners to have a preliminary understanding of the design
Update
: 2025-01-16
Size
: 334kb
Publisher
:
mike
lcd12864
Downloaded:0
the LCD12864 TEST IS OK
Update
: 2025-01-16
Size
: 33.25mb
Publisher
:
宋敏
guangshanchi
Downloaded:0
THE TEST IS OK
Update
: 2025-01-16
Size
: 16.94mb
Publisher
:
宋敏
verilogiic1121
Downloaded:0
the test is ok
Update
: 2025-01-16
Size
: 545kb
Publisher
:
宋敏
UART_16750_vhdl
Downloaded:0
UART FPGA VHDL 16750
Update
: 2025-01-16
Size
: 23kb
Publisher
:
yp
jpb_ise12migration
Downloaded:0
cycle key code
Update
: 2025-01-16
Size
: 889kb
Publisher
:
李
music
Downloaded:0
Music demo verilog file
Update
: 2025-01-16
Size
: 2kb
Publisher
:
Raz
VERILOG-Simulation
Downloaded:0
This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus us
Update
: 2025-01-16
Size
: 2.57mb
Publisher
:
Raz
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