A common interrupt system of the Verilog HDL description of the would like to know how to achieve the readers know, there will be of great help! Date : 2025-08-12
Size : 436kb
User : 陈永恒
Description of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need. Date : 2025-08-12
Size : 219kb
User : 陈永恒
Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this module. Date : 2025-08-12
Size : 14kb
User : 蓝晶
PS2 keyboard reading program, a direct call to the function can be PS2.h. In the main function of the routine in detail. Is very easy to use Date : 2025-08-12
Size : 3kb
User : 蓝晶
YCbCr turn RGB module, to apply to the project. The module can be 10bitYCbCr component video converted to 12bitRGB video, need to consume multiplier. Date : 2025-08-12
Size : 1kb
User : 张曦
CRC' s Nios soft-core processing, the system uses Altera Nios IP core for CRC algorithm, algorithm running time than the conventional CRC checkout save a lot. Date : 2025-08-12
Size : 400kb
User : lijiang
A small game in which LED(0 to 3) lights in turn. Just one LED turns on each time, and matchs the push button on our BASYS board. When LED(0 to 3) turns on, if we push the right button, then a LED(4 to 7) lights. And the Date : 2025-08-12
Size : 1.28mb
User : 大侠