VHDL-FPGA-Verilog List Page 3251

VHDL-FPGA-Verilog list

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Verilog_VHDL_Golden_Reference_Guide Downloaded：0: Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis.
Update : 2025-04-20 Size : 272kb Publisher : Nguyen Chi Nhan
Crack_Altera_Quartus61.0-9.1 Downloaded：0: Crack_Altera_Quartus61.0-9.1.rar license!!!
Update : 2025-04-20 Size : 257kb Publisher : guobo
80C51_1 Downloaded：0: 1. Asynchronous communication software simulation 2. Based on the RS-232 serial communication 3. Based on the RS-485 Multi-machine communication 4. I2C bus protocol software implementation 5. SPI bus in the MCU system to
Update : 2025-04-20 Size : 63kb Publisher : hdm
keyscan Downloaded：0: 2×8 keyboard scan---VHDL language
Update : 2025-04-20 Size : 1kb Publisher : rjy
simple_pic Downloaded：0: A common interrupt system of the Verilog HDL description of the would like to know how to achieve the readers know, there will be of great help!
Update : 2025-04-20 Size : 436kb Publisher : 陈永恒
irq_decoder Downloaded：0: Description of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need.
Update : 2025-04-20 Size : 219kb Publisher : 陈永恒
FIR Downloaded：0: FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
Update : 2025-04-20 Size : 5kb Publisher : 蓝晶
oscillograph Downloaded：0: Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this module.
Update : 2025-04-20 Size : 14kb Publisher : 蓝晶
OCMJ_LCD Downloaded：0: Large liquid crystal display programs- Jinpeng 0CMJ15X20D series. Verified by the MSP430.
Update : 2025-04-20 Size : 7kb Publisher : 蓝晶
PS2 Downloaded：0: PS2 keyboard reading program, a direct call to the function can be PS2.h. In the main function of the routine in detail. Is very easy to use
Update : 2025-04-20 Size : 3kb Publisher : 蓝晶
frame_synchronization Downloaded：0: Detection of Barker code transmission to achieve frame synchronization
Update : 2025-04-20 Size : 432kb Publisher : chenke
8051_verilog Downloaded：0: 8051 IP in verilog, which is verified in Altera9.0 environmen.
Update : 2025-04-20 Size : 50kb Publisher : dylan huang

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