VHDL-FPGA-Verilog List Page 3291

VHDL-FPGA-Verilog list

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spi_master Downloaded：0: SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps
Update : 2025-03-31 Size : 1kb Publisher : guoguo
DS_spi_ispb Downloaded：0: SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps
Update : 2025-03-31 Size : 268kb Publisher : guoguo
USB Downloaded：0: USB port design, including the driver design, and installation of software, presentation, software presentation, and working models
Update : 2025-03-31 Size : 306kb Publisher : guoguo
E1 Downloaded：0: In the International Standards Organization Open Systems Interconnect (OSI) reference model, Ethernet is the second-layer protocol. 10G Ethernet using the IEEE (Institute of Electrical and Electronics Engineers) 802.3 Et
Update : 2025-03-31 Size : 1.64mb Publisher : guoguo
pwm Downloaded：0: : Random pulse width modulation speed control system to solve the exchange of acoustic noise in a direct and effective way. Random zero vector distribution is a good random method, but the asymmetrical switching function
Update : 2025-03-31 Size : 135kb Publisher : guoguo
VerilogHDLDDS Downloaded：0: A brief introduction of direct digital frequency synthesis (DD S), the use of DDS design of arbitrary waveform generator, which can produce rectangular wave, sine wave, triangle wave, sawtooth waveform etc.
Update : 2025-03-31 Size : 195kb Publisher : guoguo
itrl Downloaded：0: Intertwined in this program is to prepare its own random interleaving can achieve any arbitrary length of the intertwined dimensions of the implementation is more than the other type has the extension
Update : 2025-03-31 Size : 4kb Publisher : justin
setup-hpld Downloaded：0: This paper describes the sub-fpga how the steady state, as well as how to calculate the metastable MTBF. The understanding of metastable helpful.
Update : 2025-03-31 Size : 548kb Publisher : 邹仁波
verilog_seg7 Downloaded：0: Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
Update : 2025-03-31 Size : 294kb Publisher : Li xiaohu
SystemVerilogforDesign2ndEdition Downloaded：0: System Verilog for design verification
Update : 2025-03-31 Size : 2.25mb Publisher : JK
contador_0a7 Downloaded：0: contador de 0 a 7 que se reinicia
Update : 2025-03-31 Size : 1kb Publisher : LoboBlanco
Nios_II_timer Downloaded：0: The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development
Update : 2025-03-31 Size : 2.01mb Publisher : huangshengqun

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