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VHDL-FPGA-Verilog list
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Key debounce program by FPGA. Verification by
Update : 2025-01-16 Size : 207kb Publisher : 啦啦啦啦

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TripAdvisor RS232 FIFO implementation for receiving data and cache
Update : 2025-01-16 Size : 1kb Publisher : xiewh

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LCD12864 driver code, pro-test available
Update : 2025-01-16 Size : 2kb Publisher : xiewh

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SPI bus IP core, can achieve half-duplex communication spi
Update : 2025-01-16 Size : 1kb Publisher : xiewh

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RS232 bus protocol ip, PC communication can be achieved
Update : 2025-01-16 Size : 1kb Publisher : xiewh

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Verilog编写,实现3DES加密过程。硬件实现
Update : 2016-08-31 Size : 10.91kb Publisher : 13739095930@163.com

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Write tutorials, as well as English ppt Source of engineering vhdl testbench
Update : 2025-01-16 Size : 11.68mb Publisher : 吴欢欢

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QAM modulator,the implementation based on FPGA,include MUL、FIRCOS and QAM generate
Update : 2025-01-16 Size : 3.73mb Publisher : 许玉淇

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Realizing serial uart interface, which can support a variety of communication speed, modlesim simulation
Update : 2025-01-16 Size : 42kb Publisher : 许玉淇

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7-segment control interface program and the initial frequency of 50MHZ clock divider program
Update : 2025-01-16 Size : 1kb Publisher : 李康康

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Based on two half-adder and an exclusive-or gate full adder (profile picture shows a half adder waveform timing simulation diagram)
Update : 2025-01-16 Size : 61kb Publisher : 李康康

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according nios ii
Update : 2025-01-16 Size : 26.81mb Publisher : jiangxin
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