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VHDL-FPGA-Verilog list
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Camera_ED
Downloaded:0
Camera interface program, collecting data the camera HDMI interface displayed on the LCD screen above
Update
: 2025-01-16
Size
: 191kb
Publisher
:
wangruiqi
sd_ctrl
Downloaded:0
Verlog implementation of the SD card control procedures, has been compiled under the quartus validation
Update
: 2025-01-16
Size
: 5kb
Publisher
:
蒋磊
vga
Downloaded:0
Link the VGA adapter located in the altera DE2board to a monitor
Update
: 2025-01-16
Size
: 695kb
Publisher
:
nisal senarathne
spi_module
Downloaded:0
FPGA and SPI
Update
: 2025-01-16
Size
: 1kb
Publisher
:
gxb
i2c_latest.tar
Downloaded:0
Synthesizable iic slave module.Modelsim simulation passed.
Update
: 2025-01-16
Size
: 1.41mb
Publisher
:
yxd
mariobros
Downloaded:0
simula la musica de mario bros por medio de sonidos mediante una fpga
Update
: 2025-01-16
Size
: 994kb
Publisher
:
jesssk
MAX197-5STATE
Downloaded:0
Use Verilog in Quartus II prepared MAX197 AD collection procedures, the system clock 50MHz. Tested fully use.
Update
: 2025-01-16
Size
: 10.35mb
Publisher
:
carlosdon
DA_TLC5620
Downloaded:0
Verilog TLV5620 program to achieve multi-channel DA module control, waveform signal output.
Update
: 2025-01-16
Size
: 4.82mb
Publisher
:
张工
AD_TLC549CP
Downloaded:0
Control TLC549 chip AD conversion, the corresponding analog into digital quantity, and digital quantity through the digital tube display.
Update
: 2025-01-16
Size
: 5.18mb
Publisher
:
张工
beep
Downloaded:0
Based quartusii design fpga buzzer experiments, testing the buzzer is working,
Update
: 2025-01-16
Size
: 2.94mb
Publisher
:
杨吉
Lab01
Downloaded:0
verilog Getting exercises, including full Verilog examples, including all documents simulation, mainly on the register definition, name mapping, RS trigger definition, etc.
Update
: 2025-01-16
Size
: 12kb
Publisher
:
gaobo
Part3
Downloaded:0
This program is developed for altera DE2 board. It consist of a real time clock with time set and reset.
Update
: 2025-01-16
Size
: 842kb
Publisher
:
nisal senarathne
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