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VHDL-FPGA-Verilog list
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Frequency meter source code, measuring range 1hz-100Mhz, seven displays three range, high precision
Update : 2025-01-17 Size : 3kb Publisher : 向润梓

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Use FPGA drives DAC0832 sampling data
Update : 2025-01-17 Size : 305kb Publisher : 林迷糊

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Even general division
Update : 2025-01-17 Size : 255kb Publisher : 林迷糊

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Using VHDL language decoding program that uses a digital display using VHDL language decoding program that uses a digital tube display
Update : 2025-01-17 Size : 226kb Publisher : 林迷糊

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VHDL language through a full adder program, which is the result of component instantiation way to achieve
Update : 2025-01-17 Size : 318kb Publisher : 林迷糊

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Counter by VHDL language, you can start counting when the count 0 to 99 and then starts counting 0
Update : 2025-01-17 Size : 282kb Publisher : 林迷糊

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An 8-bit RISC-cpu source code in modelsim simulation waveforms
Update : 2025-01-17 Size : 4.36mb Publisher : 蓝莓汁

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This document is package and pin definitions files about xilinx virtex-5 FPGA board for use v5 great help
Update : 2025-01-17 Size : 4.54mb Publisher : 梁卓君

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This used ps2 verilog language, which is the keyboard port protocol and interactive FPGA for virtex5
Update : 2025-01-17 Size : 2kb Publisher : 梁卓君

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This the interpretation of the Agreement on the keyboard and FPGA interfaces, the English have, in great detail, for people to write ps2 interface
Update : 2025-01-17 Size : 606kb Publisher : 梁卓君

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verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventional baud rate, data bits, stop bits and parity bits, input operation c
Update : 2025-01-17 Size : 6kb Publisher : 沈浩

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rs232的verilog的代码,code is based on verilog language, it is practical, we hope to help
Update : 2025-01-17 Size : 4kb Publisher : 李丽
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