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VHDL-FPGA-Verilog list
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HELLO
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frequency
Update : 2025-03-14 Size : 2kb Publisher : zoe zheng
fpga
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Verilog
Update : 2025-03-14 Size : 301kb Publisher : shang
dds_first
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Using vhdl language, and register through the adder to achieve the fpga functional dds
Update : 2025-03-14 Size : 464kb Publisher : 邢旭
IICVHDL
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NO
Update : 2025-03-14 Size : 3kb Publisher : dalianmao502
1024
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Written by C sine wave data file mif file
Update : 2025-03-14 Size : 4kb Publisher : liang
AlteraQuartusII
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Altera FPGA development software QuartusII introduction and use of manuals, help to study the development of Altera FPGA.
Update : 2025-03-14 Size : 5.19mb Publisher : 王刚
FPGA-DDC
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FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Update : 2025-03-14 Size : 98kb Publisher : 孙新荣
daima
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With VHDL language design digit stopwatch: 1, Stopwatch s time scope is 0 second ~59 minute 59.99 second, the demonstration longest time is 59 minute 59 second. 2, The time precision is 10MS. 3, The reset switch may mome
Update : 2025-03-14 Size : 5kb Publisher : SAM
daima
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With VHDL language design 8 accumulators: in eight accumulator codes in one: The accumulator is 8 accumulator logic circuit which is composed of two 4 binary system accumulator U1 and U2, U1 uses for to load in 8 accumul
Update : 2025-03-14 Size : 9kb Publisher : SAM
vhld_fpga_box
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Prepared Verilog waveform generator, can occur sine, triangle wave, square wave, you can FM
Update : 2025-03-14 Size : 261kb Publisher : ivan
QIMO
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Verilog prepared arbitrary waveform generator, with a top-level document, the output waveform
Update : 2025-03-14 Size : 5.11mb Publisher : ivan
DDS
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Quartus on the DDS, can occur sine wave, square wave, triangle wave, with the top-level documents, notes in the procedure
Update : 2025-03-14 Size : 76kb Publisher : ivan
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