VHDL-FPGA-Verilog List Page 3482

VHDL-FPGA-Verilog list

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system Downloaded：0: Vhdl based on a simple digital frequency meter design, have been debugging, can be directly used
Update : 2025-03-14 Size : 2.48mb Publisher : 郭帅
080637 Downloaded：0: As a standard display interface，VGA has been widely used．According to the designing principle ofVGA interface， Use VttDL and the FPGA ofCompany AJter’s series Cylone to design the VGA display controller．At last，the simul
Update : 2025-03-14 Size : 137kb Publisher : 吕大
vhdl_jifenping Downloaded：0: Containing odd-numbered sub-frequency code, written in simple and very easy to understand, I hope all of you help
Update : 2025-03-14 Size : 2kb Publisher : gjp_rain
serial Downloaded：0: Vhdl prepared to use the program to simulate the serial port work, send data to the PC serial port debug tools in the next showed that IPC data in digital tube display
Update : 2025-03-14 Size : 3kb Publisher : gjp_rain
vhdl Downloaded：0: The pdf in detail the calculation of the decimal floating-point rules, and procedures in vhdl decimal floating-point method, and the use of multiplication and division for all of us hope that useful
Update : 2025-03-14 Size : 203kb Publisher : gjp_rain
dds Downloaded：0: VERILOG language with the dds (DDS)
Update : 2025-03-14 Size : 102kb Publisher : 叶少朋
fft Downloaded：1: VERILOG language with the Spectrum Analyzer (FFT)
Update : 2025-03-14 Size : 4.72mb Publisher : 叶少朋
pll Downloaded：0: VERILOG language with the digital phase-locked loop PLL
Update : 2025-03-14 Size : 375kb Publisher : 叶少朋
tlc5620dac Downloaded：0: VERILOG language used to control the DAC TLC5620 procedures
Update : 2025-03-14 Size : 273kb Publisher : 叶少朋
wavegenerator Downloaded：0: Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verify is passed, the waveform in detail the d
Update : 2025-03-14 Size : 487kb Publisher : 李海明
chipscope Downloaded：0: FPGA debugging tool chipscope Make debugging faster and more convenient, reduce the FPGA development cycle -FPGA debugging tools to enable debugging chipscope change faster and more convenient, reduce development cycle o
Update : 2025-03-14 Size : 925kb Publisher : kevin
counter Downloaded：0: Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
Update : 2025-03-14 Size : 3.73mb Publisher :

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