VHDL-FPGA-Verilog List Page 3520

VHDL-FPGA-Verilog list

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fpga1 Downloaded：0: Mobile communications repeater digital filter design and FPGA realization mobile communication repeater digital filter design and FPGA realization
Update : 2025-03-12 Size : 2.23mb Publisher : 南才北往
fpga2 Downloaded：0: FPGA-based Finite Impulse Response digital filter of the research and realized FPGA-based Finite Impulse Response digital filter of the research and realized
Update : 2025-03-12 Size : 1.82mb Publisher : 南才北往
1 Downloaded：0: Graduation project handbook template- the FPGA realization of digital filters to the north to the south graduated from Design Manual template- the FPGA realization of digital filters to the north to the south
Update : 2025-03-12 Size : 10kb Publisher : 南才北往
65jie Downloaded：0: String and FIR filter design: parallel FIR filter with a fast, easy design features, but I want to use up a lot of resources. In a multi-order high-frequency sub-system design, the use of parallel structures and uneconom
Update : 2025-03-12 Size : 12kb Publisher : 南才北往
1 Downloaded：0: Programming hardware, Quartus source process, comments in detail, is your school FPGA/QuartusII good code!
Update : 2025-03-12 Size : 6.53mb Publisher : 南才北往
trafficlight Downloaded：0: Traffic light program, VHDL language, for me love Dick simulation experiment.
Update : 2025-03-12 Size : 2kb Publisher : kinglg
RD1011_rev01.2 Downloaded：0: Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog to achieve easy embedded into the design of their own. Document with
Update : 2025-03-12 Size : 212kb Publisher : pd
RealizationofdigitaldownconversionbyFPGA Downloaded：0: Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the preparation of some call a combination of IP core method of the FPGA digital dow
Update : 2025-03-12 Size : 159kb Publisher : 于银
caiyang Downloaded：1: Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control
Update : 2025-03-12 Size : 331kb Publisher : 于银
FIFO_Buffer Downloaded：0: Verilog source code of the FIFO can be integrated and applied to specific projects
Update : 2025-03-12 Size : 1kb Publisher : david
EXP4_sec Downloaded：0: Stopwatch
Update : 2025-03-12 Size : 493kb Publisher : dsds
multi Downloaded：0: VHDL Multiplier RTL code
Update : 2025-03-12 Size : 2kb Publisher : Anil Kumar Saini

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