VHDL-FPGA-Verilog List Page 361

VHDL-FPGA-Verilog list

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alu1 Downloaded：0: VHDL Code for ALU
Update : 2025-01-17 Size : 177kb Publisher : ali elgammal
digital-clock Downloaded：0: Digital clock vhdl code
Update : 2025-01-17 Size : 155kb Publisher : ali elgammal
traffic Downloaded：0: traffic vhdl code
Update : 2025-01-17 Size : 150kb Publisher : ali elgammal
kb Downloaded：0: Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
Update : 2025-01-17 Size : 3kb Publisher : God_Paine
12_24clock Downloaded：0: FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping.
Update : 2025-01-17 Size : 150kb Publisher : God_Paine
musicplayer Downloaded：0: FPGA music player based on. Can play three songs during playback to pause or resume playback, adjustable C and G tune tone, volume can be controlled manually switch songs.
Update : 2025-01-17 Size : 2.64mb Publisher : God_Paine
wenduji Downloaded：0: FPGA-based design of the thermometer. Original ambient temperature measured and displayed on the seven-segment LED, selectable Fahrenheit or Celsius temperature display, temperature exceeds a preset tone alerts after ex
Update : 2025-01-17 Size : 3.8mb Publisher : God_Paine
fft_core_test Downloaded：0: The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
Update : 2025-01-17 Size : 8.45mb Publisher : 赵庆胜
24T Downloaded：0: 24 hour cycle clock design, through the quartus module to achieve a 24 hour cycle of the clock, including analog clock pulse.
Update : 2025-01-17 Size : 864kb Publisher : 邓安华
Ripple-carry-adder Downloaded：0: Ripple carry adder using system verilog
Update : 2025-01-17 Size : 2.7mb Publisher : naim
Sequential-Multiplier Downloaded：0: sequential multiplier using system verilog
Update : 2025-01-17 Size : 2.82mb Publisher : naim
state_led_one Downloaded：0: Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-bit) FPGA using LCMXO2-1200HC-4MG132C clock 25M development board: EEFOUCS l
Update : 2025-01-17 Size : 199kb Publisher : 申奥迪

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