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VHDL-FPGA-Verilog list
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DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage signal detection/DEMO8 ADC voltage measurement/DEMO9 LCD driver circuit de
Update : 2025-01-24 Size : 719kb Publisher : wang

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Simple 32 bit Floating point Multiplier
Update : 2025-01-24 Size : 7.03mb Publisher : Rahul

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FPGA-based adaptive digital frequency meter, measuring range 1Hz-99.9MHz
Update : 2025-01-24 Size : 4kb Publisher : 王二

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vga
Update : 2025-01-24 Size : 2kb Publisher : 清洪

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Mif files generated by matlab. (Altera' s EDA software, such as maxplus, quartus used to initialize and so on rom, ram, such as the file format)
Update : 2025-01-24 Size : 1kb Publisher : 何亮

This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller,
Update : 2025-01-24 Size : 466kb Publisher : fdasfds

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Control led with clock
Update : 2025-01-24 Size : 2kb Publisher : Fl0rin

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Vhdl cod for a bus.For sp2e
Update : 2025-01-24 Size : 46kb Publisher : Fl0rin

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Vhdl cod for a clock for sp3e
Update : 2025-01-24 Size : 40kb Publisher : Fl0rin

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vhdl cod for ram.For sp3e
Update : 2025-01-24 Size : 1.07mb Publisher : Fl0rin

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MTD fixed-point floating-point simulation, fpga algorithm can be used directly in the simulation program to produce a sweep signal, the direct simulation output system frequency response function for the benefit of syste
Update : 2025-01-24 Size : 7kb Publisher : 何亮

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Altera paragraph 5 of the FPGA development board schematics, detailed information on the composition and functions of board
Update : 2025-01-24 Size : 5kb Publisher : 张建
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