VHDL-FPGA-Verilog List Page 3737

VHDL-FPGA-Verilog list

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LF_therapy Downloaded：0: low frequency therapy system control VHDL code
Update : 2025-01-24 Size : 6kb Publisher : byungchan
test_uart Downloaded：0: uart VHDL code : include tx,rx,parity bit control
Update : 2025-01-24 Size : 13kb Publisher : byungchan
Id_scanner Downloaded：0: line CCD sensor controller for ID card scanner
Update : 2025-01-24 Size : 10kb Publisher : byungchan
eth_top Downloaded：0: Logic-based Ethernet instrument development, logic-based Ethernet development instrument
Update : 2025-01-24 Size : 5kb Publisher : 田峪宋
VHDL Downloaded：0: Implement a 10-second countdown timer and require 8*8 to display timing results. On the QuartusII platform, the design procedure and simulation title are required, and the experimental results are downloaded to the exper
Update : 2025-01-24 Size : 395kb Publisher : li
digtal Downloaded：0: Digital clock basic VHDL source code.
Update : 2025-01-24 Size : 2kb Publisher : jm2005
fpga Downloaded：0: Wireless optical communication technology has the communications capacity, many of the benefits of higher transmission rates, in many occasions have important applications in modern communication technologies are a hot r
Update : 2025-01-24 Size : 190kb Publisher : 朱雯
VHDLTESTBENCH Downloaded：0: Article describes how to use VHDL simulation Writing incentive source.
Update : 2025-01-24 Size : 9.16mb Publisher : 朱雯
FPGAphaselockedloopdesign Downloaded：0: Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
Update : 2025-01-24 Size : 280kb Publisher : 朱雯
niosII_cyclone_1c20 Downloaded：0: IIR, FIR, FFT modular design of the routines can be used as IP use, useful for beginners
Update : 2025-01-24 Size : 69kb Publisher : 石林
QuartusIIandModelSim Downloaded：0: This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, con
Update : 2025-01-24 Size : 271kb Publisher : 朱雯
n2cpu_nii51004 Downloaded：0: NIOSII CPU design examples, including AVOLON bus characteristics and timing requirements
Update : 2025-01-24 Size : 135kb Publisher : 石林

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