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VHDL-FPGA-Verilog list
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FIFO using Verilog language design, in the FPGA to achieve 32X8FIFO function
Update : 2025-01-22 Size : 171kb Publisher : sky

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UART classical procedures, UART VHDL design language, to help everyone study UART knowledge
Update : 2025-01-22 Size : 11kb Publisher : xzq

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Asynchronous Receiver Transmitter apply VHDL design language, are a good knowledge of study UART routines
Update : 2025-01-22 Size : 6kb Publisher : xzq

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UART study of knowledge, classical UART procedures, UART VHDL design language
Update : 2025-01-22 Size : 4.86mb Publisher : xzq

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It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write cycle are supported
Update : 2025-01-22 Size : 3kb Publisher : Pankaj

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< < Proficient in core technology VerilogHDL IC design examples explain> > Appendix 1 of the book source code.
Update : 2025-01-22 Size : 509kb Publisher : 李德胜

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SDRAM controller provided by Altera in Verilog HDL
Update : 2025-01-22 Size : 792kb Publisher : machenghai

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Sine wave output of the VHDL, the use of VHDL prepared already through debugging
Update : 2025-01-22 Size : 572kb Publisher : zhang

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ARM7 core, vhdl source code form, not the many good things.
Update : 2025-01-22 Size : 69kb Publisher : guodelei

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sata_device_model, to make the hard disk controller has a friend help
Update : 2025-01-22 Size : 16.61mb Publisher :

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32-bit_multiplier_model procedures, can be directly used to use
Update : 2025-01-22 Size : 2kb Publisher :

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Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
Update : 2025-01-22 Size : 102kb Publisher :
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