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VHDL-FPGA-Verilog list
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caijika
Downloaded:0
FPGA-based design of frame grabbers and related note
Update
: 2025-01-18
Size
: 146kb
Publisher
:
test
Downloaded:0
Several Example FPGA design contest
Update
: 2025-01-18
Size
: 1.66mb
Publisher
:
vhdl_design
Downloaded:0
Design a complete digital electronic clock design, including the principle of introduction, program design, waveform simulation
Update
: 2025-01-18
Size
: 145kb
Publisher
:
Daili
myDPll
Downloaded:0
I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
Update
: 2025-01-18
Size
: 1kb
Publisher
:
杨广
DCT
Downloaded:0
altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
Update
: 2025-01-18
Size
: 14.69mb
Publisher
:
alison
asynch_fifo
Downloaded:0
FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
Update
: 2025-01-18
Size
: 1004kb
Publisher
:
alison
an_dcfifo_top_restored
Downloaded:0
alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Update
: 2025-01-18
Size
: 907kb
Publisher
:
alison
DE2_LCM_CCD
Downloaded:0
In altera DE2 development board collecting images, lcd display to the original procedure.
Update
: 2025-01-18
Size
: 3.28mb
Publisher
:
alison
fpga_intr
Downloaded:0
Jane FPGA: FPGA describes the basic concepts, structure, development
Update
: 2025-01-18
Size
: 188kb
Publisher
:
zzgy1029
PS2_verilog_source
Downloaded:0
In VHDL development environment, with regard to the agreement PS2 verilog source code
Update
: 2025-01-18
Size
: 1kb
Publisher
:
clwclwclw
MFSK_VHDL
Downloaded:0
Multi-band digital frequency modulation (MFSK) system VHDL procedures
Update
: 2025-01-18
Size
: 1kb
Publisher
:
zhang
fir_16
Downloaded:0
fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
Update
: 2025-01-18
Size
: 8kb
Publisher
:
wq
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