VHDL-FPGA-Verilog List Page 3906

VHDL-FPGA-Verilog list

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work3CNT4BDECL7S Downloaded：0: 7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data p
Update : 2025-01-18 Size : 81kb Publisher : lkiwood
work4dvf Downloaded：0: NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different sub-frequency ratio, NC prescaler value can be used include parallel preset counter ad
Update : 2025-01-18 Size : 33kb Publisher : lkiwood
work5FREQTEST Downloaded：0: 8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signa
Update : 2025-01-18 Size : 239kb Publisher : lkiwood
work6ADCINT Downloaded：0: ADC0809频实 ADC0809CMOS8位A/D 转片8 模饪?兀煽8模械一转校转时约 100us要藕校START 转藕牛叩平效ALE3位通选ADDCADDBADDA藕诺藕拧模某一耍 IN1IN23位藕选瘢
Update : 2025-01-18 Size : 28kb Publisher : lkiwood
vhdl Downloaded：0: Experimental _EDA experimental guidance notes EDA books EDA technology and VHDL in Chapter 3 of EDA technologies utility EAD Technology and Practice Guide. And so on Information
Update : 2025-01-18 Size : 20.06mb Publisher : lkiwood
jilytimer Downloaded：0: VHDL Pang Sung-wife of mother
Update : 2025-01-18 Size : 223kb Publisher : 郑礼龙
VHDLshili44 Downloaded：0: VHDL subprogram, I collected to compare commonly used code
Update : 2025-01-18 Size : 42kb Publisher : 郑礼龙
Verilog_Design Downloaded：0: Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.
Update : 2025-01-18 Size : 3kb Publisher : leniux
vhdlsample Downloaded：0: There is some examples of VHDL, we can look pretty good on the U.S. improve the level VHDL good.
Update : 2025-01-18 Size : 165kb Publisher : leniux
68013FIFOIN Downloaded：0: Verilog HDL prepared CY7C68013 SLAVE FIFO interface program, the actual test can be used. Keep pace with the digital machine can be directly connected to transmit data.
Update : 2025-01-18 Size : 649kb Publisher : huanghui
traffic_light Downloaded：0: Realize a simple traffic lights at the crossroads of the verilog hdl source code, can be achieved
Update : 2025-01-18 Size : 1kb Publisher : 王新
verilog Downloaded：0: The Verilog sourceinsight plug-ins
Update : 2025-01-18 Size : 3kb Publisher : 楚歌

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