VHDL-FPGA-Verilog List Page 3933

VHDL-FPGA-Verilog list

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txxclock Downloaded：0: VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display
Update : 2025-01-18 Size : 301kb Publisher :
div Downloaded：0: The VHDL source for the prescaler languages, W-4b in the teaching platform validated
Update : 2025-01-18 Size : 108kb Publisher :
LIGHT Downloaded：0: author: Suntion Tang date: 2008-6-7 two warning modify: By Suntion Tang at 2008-6-14 description: the top-level documents, as a result of this system is simple, and not more than the bottom of a document, they give up th
Update : 2025-01-18 Size : 172kb Publisher :
6713emiftofpgatopci Downloaded：0: 6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA
Update : 2025-01-18 Size : 2kb Publisher : 丁科
ISE Downloaded：0: Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.
Update : 2025-01-18 Size : 48.96mb Publisher : wl
hdl Downloaded：1: Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Update : 2025-01-18 Size : 6kb Publisher : 刘义春
Cursor Downloaded：0: ALTERA the DE2 platform VGA interface applications, from top to bottom KEY0-KEY3 about control, so that the screen cursor by the Verilog description.
Update : 2025-01-18 Size : 761kb Publisher : 徐朝凯
Traffic Downloaded：0: Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.
Update : 2025-01-18 Size : 257kb Publisher : 徐朝凯
Time Downloaded：0: ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
Update : 2025-01-18 Size : 595kb Publisher : 徐朝凯
PWMtest Downloaded：0: Using VHDL realize CPLD (EMP240T100C5) of the PWM output
Update : 2025-01-18 Size : 170kb Publisher : ZXQ
VGA_test50m Downloaded：1: Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen
Update : 2025-01-18 Size : 225kb Publisher : ZXQ
recuart_50m Downloaded：0: Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure
Update : 2025-01-18 Size : 197kb Publisher : ZXQ

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