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VHDL-FPGA-Verilog list
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Changes in operating frequency IP, I hope some people like! Wrote it myself, under the need!
Update : 2025-01-16 Size : 4kb Publisher : xzb

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Another reading of 429 yards to operate IP, when the military was very useful, I hope some people like!
Update : 2025-01-16 Size : 2kb Publisher : xzb

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Another sent 429 to operate IP, the military was very useful, I hope some people like!
Update : 2025-01-16 Size : 3kb Publisher : xzb

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Electronic code lock, enter the three error stopping further importation. Password setting process.
Update : 2025-01-16 Size : 71kb Publisher : 李立

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Advance Cargo Information storage, process control, handle coins, and the balance calculation shows that functions.
Update : 2025-01-16 Size : 140kb Publisher : 李立

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Electronic clock, procedures clearly structured, has a detailed description of the functional simulation, you can watch one.
Update : 2025-01-16 Size : 58kb Publisher : 李立

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VHDL procedures flower contains: top-level procedures, scale generator procedures, numerical control frequency module procedures and module procedures performed automatically
Update : 2025-01-16 Size : 49kb Publisher : 李立

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When the elevator stopped on the first floor, received the request signal c_d3, c_d2, c_u4 and d6, and the write request signal corresponding register. led display elevator floor led_d, led-c_u and led_c_d shows the user
Update : 2025-01-16 Size : 159kb Publisher : 李立

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8.12 MASK modulation procedures and VHDL simulation, after increasing, with hdl completed mask compiler and simulation
Update : 2025-01-16 Size : 38kb Publisher : 空军

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Clock program for FPGA development board in the LCD1602 display hours, minutes, seconds, tenth of seconds
Update : 2025-01-16 Size : 2kb Publisher : lijingfeng

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Update : 2025-01-16 Size : 1.53mb Publisher :

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The program realization of a digital clock, adjust the time zone feature, adjust time, the location of the corresponding display flashes. CLR to zero client, the key to
Update : 2025-01-16 Size : 673kb Publisher : 李东
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