VHDL-FPGA-Verilog List Page 3987

VHDL-FPGA-Verilog list

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gff_int_mul Downloaded：1: application of a galois field multiplication and normal multiplication
Update : 2025-01-16 Size : 178kb Publisher :
Verilog_example Downloaded：0: This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 se
Update : 2025-01-16 Size : 1.02mb Publisher : 朱秋玲
Crack_QII70 Downloaded：0: quartusII7.0license decoder
Update : 2025-01-16 Size : 17kb Publisher : fanghao
4bit.elock Downloaded：0: 4 electronic code locks, has detailed the steps that have functional simulation map, worth a visit
Update : 2025-01-16 Size : 448kb Publisher : 李里
elock.vhdl.pdf Downloaded：0: A VHDL-based electronic locks thesis design, have some code that can be down as a reference.
Update : 2025-01-16 Size : 360kb Publisher : 李里
elock.555.pdf Downloaded：0: Single-chip electronic locks, mainly used in electronic circuit knowledge, it is necessary to Friend Please note that under the click.
Update : 2025-01-16 Size : 89kb Publisher : 李里
elock.verilog.pdf Downloaded：0: Verilog-based electronic locks thesis introduction. Some program code.
Update : 2025-01-16 Size : 288kb Publisher : 李里
example.verilog.pdf Downloaded：0: On a large number of examples of Verilog, through mastery of these examples, you can design any commonly used procedures.
Update : 2025-01-16 Size : 111kb Publisher : 李里
verilog Downloaded：0: Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of
Update : 2025-01-16 Size : 156kb Publisher : luojinwen
ModelSim_Tutorial_V5.4 Downloaded：0: This is the agency on how to use Mentor
Update : 2025-01-16 Size : 688kb Publisher : 许京哲
Design_Compiler_FPGA_Design_Flow Downloaded：0: This is about how to use the Design Compiler_FPGA Design Flow software manuals.
Update : 2025-01-16 Size : 56kb Publisher : 许京哲
cpld Downloaded：0: 4CAN card on the hardware procedures, prepared by VHDL. Is 4 CAN BUS
Update : 2025-01-16 Size : 610kb Publisher : 徐

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