VHDL-FPGA-Verilog List Page 4076

VHDL-FPGA-Verilog list

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cic Downloaded：0: Verilog code written by CIC filter procedures, including 4 times the extraction CIC filter and the CIC interpolation filter two
Update : 2025-01-12 Size : 22kb Publisher : 桃子
cfft Downloaded：0: CFFT is a data width and the base points can be configured 4 FFT core, using VHDL realize
Update : 2025-01-12 Size : 165kb Publisher :
aes_core.tar Downloaded：0: AES realize the Verilog for hardware implementation of encryption algorithms!
Update : 2025-01-12 Size : 68kb Publisher : 刘志刚
ata.tar Downloaded：0: Hard disk interface hardware implementation, VHDL and Verilog is absorbed with documentation!
Update : 2025-01-12 Size : 813kb Publisher : 刘志刚
ads7844 Downloaded：0: The source of the introduction ADS7844 AD conversion of the VHDL controller chip.
Update : 2025-01-12 Size : 1.32mb Publisher : 周生
firfilter Downloaded：0: The realization of a FIR filter, type-type algorithm based on direct input data width: 8-bit output data width: 16 bands: 16 bands converted by the filter (shifted to right 16-bit) for the characteristic parameters: h [0
Update : 2025-01-12 Size : 1.57mb Publisher : Eric
firfilter_da Downloaded：0: err
Update : 2025-01-12 Size : 1.95mb Publisher : Eric
fsm Downloaded：0: Detection of input data of
Update : 2025-01-12 Size : 6kb Publisher : Eric
MaxplusII123 Downloaded：0: MaxplusII (Chinese) Quick Start, the CPLD or FPGA-learning has helped
Update : 2025-01-12 Size : 256kb Publisher : 柱陈
QuartusIIUserGuide Downloaded：0: QuartusII User s Guide for Learning Altera Corporation FPGA friends, would be helpful!
Update : 2025-01-12 Size : 825kb Publisher : 王刚
eeprom Downloaded：0: EEPROM of the Verilog HDL source code, including reading and writing EEPROM! Quartus II5.0 platform test!
Update : 2025-01-12 Size : 509kb Publisher :
naozhong Downloaded：0: Using simulation to compile maxplus adopted. Digital alarm clock design, their timing, counting alarm.
Update : 2025-01-12 Size : 140kb Publisher : 李志伟

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