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VHDL-FPGA-Verilog list
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Divider based on the NC VHDL design source code and simulation
Update : 2025-01-12 Size : 98kb Publisher : hlj1232123

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Based on the VHDL language taxi billing source code and simulation
Update : 2025-01-12 Size : 27kb Publisher : hlj1232123

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VHDL-based multi-language source waveform generator design and simulation
Update : 2025-01-12 Size : 10kb Publisher : hlj1232123

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pci interface Verilog source code, the definition of a pci interface pins required by all
Update : 2025-01-12 Size : 4kb Publisher : david

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Mac sublayer 10M/100M Ethernet 802.3 protocol source code, including half-duplex and full duplex.
Update : 2025-01-12 Size : 120kb Publisher : fiercewind

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Timing verilog description of QVGA
Update : 2025-01-12 Size : 1kb Publisher : vico

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QVGA display QVGA display white box white box
Update : 2025-01-12 Size : 1kb Publisher : vico

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QVGA display white box test bench procedures
Update : 2025-01-12 Size : 1kb Publisher : vico

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Ethernet 16B/20B source code including the encoder and decoder functions
Update : 2025-01-12 Size : 727kb Publisher : asd

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Prepared using Verilog CRC check codes, including 8, 12, 16, 32, a very practical
Update : 2025-01-12 Size : 11kb Publisher : asd

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Using VHDL language programmable chip serial 8251, including all of the features of 8251
Update : 2025-01-12 Size : 359kb Publisher : asd

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Using VHDL language programmable parallel interface chip 8255, including all of the features of 8255
Update : 2025-01-12 Size : 221kb Publisher : asd
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