VHDL-FPGA-Verilog List Page 4105

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .00 .01 .02 .03 .04 4105.06 .07 .08 .09 .10 ... 4311 »

GRAYcode Downloaded：0: Binary code is converted to Gray code, the entire project, including the waveform files in the Quartus on direct simulation.
Update : 2025-01-12 Size : 29kb Publisher : 桃子
jkchu Downloaded：0: jk flip-flop, try to edit their own, using state machine to achieve, you can
Update : 2025-01-12 Size : 80kb Publisher : 谢小川
fenpin Downloaded：0: Divider, try to edit their own, 20 and 40 sub-band can be
Update : 2025-01-12 Size : 91kb Publisher : 谢小川
quanjia Downloaded：0: Full adder, the use of macro functional blocks, together with simulation waveform diagram
Update : 2025-01-12 Size : 90kb Publisher : 谢小川
zhuangtai Downloaded：0: State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn
Update : 2025-01-12 Size : 98kb Publisher : 谢小川
pcm1804_i2s_data_adjust2 Downloaded：0: I2S for pcm1804 adjusted data, so that I2S audio synchronization and FIFO does not overflow. Can automatically determine the FIFO- the state, by adjusting the output from the FIFO in the number of data in order to make t
Update : 2025-01-12 Size : 2kb Publisher : WQL
amba_verilog Downloaded：1: IC design, arm within the realization of the source AMBA bridge, verilog language,
Update : 2025-01-12 Size : 18kb Publisher : 伊路发
viterbi Downloaded：0: Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Update : 2025-01-12 Size : 61kb Publisher : yaoyongshi
CIC Downloaded：0: Introduced the integral comb filter (CIC) design, there are procedures for compressed packets flow chart, using verilogHDL prepared on the ModelSim simulation results can be achieved very good
Update : 2025-01-12 Size : 150kb Publisher : yaoyongshi
CORDIC Downloaded：0: Introduced the CORDIC digital computer design, using the verilogHDL, can be achieved on the ModelSim simulation, compressed package that contains the work of CORDIC structure diagram, a more detailed
Update : 2025-01-12 Size : 138kb Publisher : yaoyongshi
add Downloaded：0: Introduced carry_chain_adder, carry_skip_adder, ipple_carry_adder three commonly used adder, using verilogHDL language, the use of ModelSim simulation software, compressed packet contains flowchart
Update : 2025-01-12 Size : 364kb Publisher : yaoyongshi
divider Downloaded：0: Introduced the divider design, using verilogHDL language, the use of ModelSim simulation, compressed package that contains a flow chart
Update : 2025-01-12 Size : 82kb Publisher : yaoyongshi

« 1 2 ... .00 .01 .02 .03 .04 4105.06 .07 .08 .09 .10 ... 4311 »

Search in result